公开(公告)号：HK1201354A1

公开(公告)日：2015-08-28

申请号：HK15101821

申请日：2015-02-18

Applicant: IBM

Inventor： GSCHWIND MICHAEL KARL MK

IPC: G06F20060101

Abstract: Emulation of instructions that include non-contiguous specifiers is facilitated. A non-contiguous specifier specifies a resource of an instruction, such as a register, using multiple fields of the instruction. For example, multiple fields of the instruction (e.g., two fields) include bits that together designate a particular register to be used by the instruction. Non-contiguous specifiers of instructions defined in one computer system architecture are transformed to contiguous specifiers usable by instructions defined in another computer system architecture. The instructions defined in the another computer system architecture emulate the instructions defined for the one computer system architecture.

公开(公告)号：HK1201372A1

公开(公告)日：2015-08-28

申请号：HK15101823

申请日：2015-02-18

Applicant: IBM

Inventor： BRADBURY JONATHAN DAVID JD ,  GSCHWIND MICHAEL KARL MK ,  SCHWARZ ERIC MARK EM ,  SLEGEL TIMOTHY T ,  JACOBI CHRISTIAN C

IPC: G11C20060101

Abstract: A Load Count to Block Boundary instruction is provided that provides a distance from a specified memory address to a specified memory boundary. The memory boundary is a boundary that is not to be crossed in loading data. The boundary may be specified a number of ways, including, but not limited to, a variable value in the instruction text, a fixed instruction text value encoded in the opcode, or a register based boundary; or it may be dynamically determined.

公开(公告)号：HK1210845A1

公开(公告)日：2016-05-06

申请号：HK15111616

申请日：2015-11-25

Applicant: IBM

Inventor： BRADBURY JONATHAN DAVID JD ,  SCHWARZ ERIC MARK EM ,  SLEGEL TIMOTHY T ,  GSCHWIND MICHAEL KARL MK

IPC: G06F20060101

公开(公告)号：HK1201353A1

公开(公告)日：2015-08-28

申请号：HK15101820

申请日：2015-02-18

Applicant: IBM

Inventor： BRADBURY JONATHAN DAVID JD ,  GSCHWIND MICHAEL KARL MK ,  SLEGEL TIMOTHY T ,  SCHWARZ ERIC MARK EM ,  JACOBI CHRISTIAN C

IPC: G06F20060101

Abstract: A Load to Block Boundary instruction is provided that loads a variable number of bytes of data into a register while ensuring that a specified memory boundary is not crossed. The boundary is dynamically determined based on a specified type of boundary and one or more characteristics of the processor executing the instruction, such as cache line size or page size used by the processor.

公开(公告)号：HK1201352A1

公开(公告)日：2015-08-28

申请号：HK15101816

申请日：2015-02-18

Applicant: IBM

Inventor： BRADBURY JONATHAN DAVID JD ,  GSCHWIND MICHAEL KARL MK ,  SLEGEL TIMOTHY T ,  SCHWARZ ERIC MARK EM ,  JACOBI CHRISTIAN C

IPC: G06F20060101

Abstract: A Load to Block Boundary instruction is provided that loads a variable number of bytes of data into a register while ensuring that a specified memory boundary is not crossed. The boundary may be specified a number of ways, including, but not limited to, a variable value in the instruction text, a fixed instruction text value encoded in the opcode, or a register based boundary.