公开(公告)号：US3848259A

公开(公告)日：1974-11-12

申请号：US41112373

申请日：1973-10-30

Applicant: IBM

Inventor： HERRELL D

IPC: H01L39/22 ,  H03K19/195 ,  H01L11/00 ,  H01L3/00

CPC classification number: H01L39/223 ,  H03K19/1952 ,  Y10S505/874

Abstract: A Josephson tunnelling device with means for producing magnetic fields which intercept the device. These fields establish screening currents in the device. The field producing means includes means for establishing a substantially 1:1 distribution of gate current through the device and the screening current. A particular embodiment is a Josephson logic gate having multiple control lines shaped to insure that current in each control line has the same effect on the junction as current in every other control line. Superconducting layers forming a Josephson tunnel device are sufficiently long to allow the gate currents and screening currents to spread evenly across the width of the Josephson junction.

Abstract translation: 约瑟夫森隧道装置，其具有用于产生拦截装置的磁场的装置。 这些领域在设备中建立了筛选电流。 场产生装置包括用于建立栅极电流通过器件和屏蔽电流的大致1:1分布的装置。 特定实施例是约瑟夫逊逻辑门，其具有多个控制线，其形状确保每个控制线中的电流与每隔一个控制线中的电流在结上具有相同的效果。 形成约瑟夫逊隧道装置的超导层足够长以允许栅极电流和屏蔽电流在约瑟夫逊结的宽度上均匀分布。

公开(公告)号：US3795977A

公开(公告)日：1974-03-12

申请号：US3795977D

申请日：1971-12-30

Applicant: IBM

Inventor： BERKENBLIT M ,  COLE J ,  PARK K ,  REISMAN A ,  HERRELL D ,  LIGHT T

IPC: G11C11/41 ,  G11C11/39 ,  G11C13/00 ,  H01C7/00 ,  H01C7/108 ,  H01L29/86 ,  H01L45/00 ,  B01J17/00

CPC classification number: G11C13/0007 ,  G11C11/39 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2213/31 ,  H01C7/108 ,  H01L27/2472 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1633 ,  Y10T29/413

Abstract: Methods for providing bistable resistors fabricated from insulators exhibiting a plurality of impedance states, an example of which is a niobium-niobium oxide device. These methods use thermal treatment and chemical reduction of amorphous metal oxides to form an active filament in each device. In one method consumable metal dots are located on the amorphous metal oxide and the oxide is then annealed in an inert gas, preferably having a small percentage of oxygen therein. This causes an oxidationreduction reaction in the oxide regions directly beneath the metal dots. In a second method, the metal oxide layer is covered with a protective insulating mask except in selected portions, and the exposed metal oxide portions are then annealed in a reducing gas atmosphere. In each method, the top electrodes are deposited on the selectively reduced portions of the metal oxide layer and then the devices are electrically formed using only a small voltage (2 or 3 volts).

Abstract translation: 提供由表现出多个阻抗状态的绝缘体制造的双稳态电阻器的方法，其实例是铌 - 氧化铌器件。 这些方法使用无定形金属氧化物的热处理和化学还原来在每个装置中形成活性丝。 在一种方法中，可消耗金属点位于无定形金属氧化物上，然后氧化物在惰性气体中退火，优选在其中具有小百分比的氧。 这导致在金属点正下方的氧化物区域发生氧化还原反应。 在第二种方法中，除了选定的部分之外，金属氧化物层被保护绝缘掩模覆盖，然后暴露的金属氧化物部分在还原气体气氛中退火。 在每种方法中，顶部电极沉积在金属氧化物层的选择性还原部分上，然后仅使用小的电压（2或3伏特）电气地形成器件。

公开(公告)号：US3784854A

公开(公告)日：1974-01-08

申请号：US3784854D

申请日：1972-12-29

Applicant: IBM

Inventor： HERRELL D

IPC: G06F7/38 ,  H03K19/195 ,  H03K17/80 ,  H03K19/10

CPC classification number: G06F7/381 ,  H03K19/1952 ,  Y10S505/861

Abstract: A binary adder using Josephson devices for the sum and carry gates is disclosed. A gating current Ig1 is applied to a Josephson device operating as a sum gate, and a gating current Ig2 is applied to a Josephson device operating as a carry gate. Each of said Josephson devices switches from v 0 to v NOT = 0 when the control current applied thereto lowers the critical gating current below the applied gating currents Ig1 and Ig2 respectively. The binary bits to be added, A, B, and Carry, C, from the prior stage, are applied to the Josephson devices as control currents Ix. The sum gate switches to v NOT = O, corresponding to a sum bit output, S, when the total control current is Ix or 3I x. The carry gate switches to v NOT = o, corresponding to a carry bit output, C, when the total control current is 2Ix or 3Ix.

Abstract translation: 公开了使用约瑟夫逊器件用于和和进位门的二进制加法器。 将门控电流Ig1施加到作为和门操作的约瑟夫逊器件，并且将门控电流Ig2施加到作为进位栅极操作的约瑟夫逊器件。 当施加的控制电流降低低于施加的门控电流Ig1和Ig2的临界门控电流时，所述约瑟夫逊器件中的每一个器件从v = 0切换到v NOTEQUAL 0。 将要添加的二进制位A，B和Carry，C从前一级施加到约瑟夫逊器件作为控制电流Ix。 当总控制电流为Ix或3I x时，和门切换到v NOTEQUAL O，对应于和位输出S。 当总控制电流为2I x或3I x时，进位门切换到v NOTEQUAL o，对应于进位位输出C。