公开(公告)号：CA1309199C

公开(公告)日：1992-10-20

申请号：CA579392

申请日：1988-10-05

Applicant: IBM

Inventor： BUTLER NICHOLAS D ,  HOMEWOOD BRIAN C ,  LARKY STEVEN P

IPC: G06F3/153 ,  G06T9/00 ,  G09G1/00 ,  G09G1/02 ,  G09G5/00 ,  G09G5/36 ,  G09G5/39 ,  G09G5/395 ,  G09G1/16

Abstract: BIT GATING FOR EFFICIENT USE OR RAMS IN VARIABLE PLANE DISPLAYS Apparatus for serializing 2M parallel outputs of an all points addressable memory into successive data groups, each data group corresponding to a respective value for a pixel in an image wherein the bit-length of the pixel value is selectable, the apparatus comprising: a gate circuit having (i) 2M parallel input junctions connected to the outputs of the memory and (ii) 2N output junctions, wherein the gate circuit selectively converts each set of 2M parallel inouts at said input junctions into 2M-n successive data groups, each group having a bit-length of 2n bits, wherein each group is transmitted to 2n of the 2N out put junctions; and a communication element for conveying to the gate circuit a signal which controls the bit-length 2n of data groups, wherein n is an integer 1 ? n ? N ? M.