公开(公告)号：JPH10326879A

公开(公告)日：1998-12-08

申请号：JP13170898

申请日：1998-05-14

Applicant: IBM

Inventor： HASSEIN ABRAHIM HANAFI ,  IRVIND KUMAR ,  WORDEMAN MATTHEW R

IPC: H01L29/78 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/732 ,  H01L31/119

Abstract: PROBLEM TO BE SOLVED: To provide an improve FET/capacitor structure which is suitable for high density integration. SOLUTION: New structures of a vertical type FET 10 and a capacitor 24 forming a memory cell can be employed in a basic building block of a memory chip, such as a high-density DRAM. A first electrode 23 of the capacitor 24 is connected to a drain 15 of a transistor. A source 13 of the transistor is connected to a source of another transistor. A gate 14 is connected to a work line 26, and a second electrode 21 of the capacitor 24 is connected to a bit line 21.