公开(公告)号：WO0229818A3

公开(公告)日：2003-06-19

申请号：PCT/EP0110937

申请日：2001-09-21

Applicant: IBM ,  IBM DEUTSCHLAND

Inventor： HSU LOUIS LU-CHEN ,  PARENT RICHARD MICHAEL ,  WORDEMAN MATTHEW R

IPC: G11C5/14 ,  G11C8/08 ,  G11C11/406 ,  G11C11/4074

CPC classification number: G11C11/406 ,  G11C5/146 ,  G11C8/08 ,  G11C11/4074 ,  G11C2207/104

Abstract: A system and method for considerable reduction of power consumption in memory circuits implementing Vbb (array body bias) and Vwl (negative word line) voltage generators. The system comprises switching off the negative WL generator during sleep or standby mode, so that no power is consumed. A relaxed refresh operation is carried out and the negative WL is powered by the Vbb generator. The noise coupled to the negative WL supply from BL swing is reduced due to the joint Vbb-Vwl decoupling scheme. In the active mode, the Vbb and Vneg are separated to avoid any cross-over noise and to maintain design flexibility. During power-on period, the ramp-up rate of Vbb level is improved by the Vwl generator. The advantages may be summarized as: (1) simpler Vbb generator design, (2) much smaller Vbb generator size, (3) reduced Vbb power, (4) no stand-by current from Vwl generator, (5) low decoupling noise for Vwl level during stand-by or sleep mode, (6) enhanced ramp-up rate for Vbb during power-on, (7) no cross-over noise between Vbb and Vwl during active mode, and (8) design flexibility of Vbb and Vwl in the active mode. The principles and advantages of the invention may be applied to any two or more DC generator systems, negative or positive.

Abstract translation: 用于实现Vbb（阵列体偏置）和Vwl（负字线）电压发生器的存储电路中的功耗的显着降低的系统和方法。 该系统包括在睡眠或待机模式期间关闭负WL发生器，使得不消耗电力。 执行松弛的刷新操作，负的WL由Vbb发生器供电。 由于联合Vbb-Vwl去耦方案，耦合到BL摆幅的负WL电源的噪声减小。 在活动模式下，Vbb和Vneg被分离，以避免任何交叉噪声并保持设计灵活性。 在上电期间，Vwl发生器提高了Vbb电平的上升速率。 其优点可概括为：（1）Vbb发电机设计更简单，（2）Vbb发电机尺寸小得多，（3）Vbb功率降低，（4）Vwl发电机无待机电流，（5）低去耦噪声 待机或休眠模式下的Vwl电平，（6）上电时Vbb的提升速率，（7）活动模式期间Vbb和Vwl之间无交叉噪声，（8）Vbb和Vbb的设计灵活性 Vwl处于活动模式。 本发明的原理和优点可以应用于任何两个或多个DC发电机系统，负极或正极。

公开(公告)号：JPH1117001A

公开(公告)日：1999-01-22

申请号：JP16022198

申请日：1998-06-09

Applicant: IBM

Inventor： MARK A JEISO ,  MANDELMAN JACK A ,  TONTI WILLIAM R ,  WORDEMAN MATTHEW R

IPC: H01L21/20 ,  H01L21/76 ,  H01L21/762 ,  H01L21/84 ,  H01L27/12

Abstract: PROBLEM TO BE SOLVED: To provide an SOI(silicon on Insulator)/bulk hybrid semiconductor substrate. SOLUTION: A semiconductor device has SOI regions 120 and bulk regions 122. In single crystal semiconductor regions, conductive spacers 124 are provided to electrically connect the SOI regions to the ground, thereby overcoming the floating body effect. Insulative spacers 126 are formed on the conductive spacers 124 to electrically separate the SOI regions 120 from the bulk regions 122. In manufacturing process of these regions, a sacrificial polishing layer is deposited to the epitaxially grown single crystal bulk regions, and there is no need to selectively grow.

公开(公告)号：JPH10326879A

公开(公告)日：1998-12-08

申请号：JP13170898

申请日：1998-05-14

Applicant: IBM

Inventor： HASSEIN ABRAHIM HANAFI ,  IRVIND KUMAR ,  WORDEMAN MATTHEW R

IPC: H01L29/78 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/732 ,  H01L31/119

Abstract: PROBLEM TO BE SOLVED: To provide an improve FET/capacitor structure which is suitable for high density integration. SOLUTION: New structures of a vertical type FET 10 and a capacitor 24 forming a memory cell can be employed in a basic building block of a memory chip, such as a high-density DRAM. A first electrode 23 of the capacitor 24 is connected to a drain 15 of a transistor. A source 13 of the transistor is connected to a source of another transistor. A gate 14 is connected to a work line 26, and a second electrode 21 of the capacitor 24 is connected to a bit line 21.

公开(公告)号：WO0199160A3

公开(公告)日：2002-10-17

申请号：PCT/US0119684

申请日：2001-06-20

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： SCHNABEL RAINER FLORIAN ,  RADENS CARL J ,  LANDIS HOWARD ,  PARK YOUNG JIN ,  KOTECKI DAVID ,  REITH ARMIN M ,  TRICKLE WAYNE ,  WORDEMAN MATTHEW R

IPC: H01L27/108

CPC classification number: H01L27/10805 ,  H01L27/10808

Abstract: A semiconductor memory device (100), in accordance with the present invention, includes a substrate having a major surface including an array region (102) and a support region (104). The array region includes memory cell structures (106) having a first height above the major surface of the substrate. The support area includes dummy structures (119) formed therein having a second height above the major surface. A dielectric layer (118) is formed over the memory cell structures in the array region and the dummy structures in the support region such that a top surface (122) of the dielectric layer is substantially planar wherein topographical features are substantially eliminated on the dielectric layer across the array region and the support region.

Abstract translation: 根据本发明的半导体存储器件（100）包括具有包括阵列区域（102）和支撑区域（104）的主表面的衬底。 阵列区域包括在衬底的主表面上方具有第一高度的存储单元结构（106）。 支撑区域包括形成在其中的在主表面上方具有第二高度的虚拟结构（119）。 在阵列区域中的存储单元结构和支撑区域中的虚拟结构之间形成电介质层（118），使得电介质层的顶表面（122）基本上是平面的，其中在介电层上基本上消除了形貌特征 跨越阵列区域和支撑区域。

公开(公告)号：WO0133706A9

公开(公告)日：2002-07-04

申请号：PCT/US0029820

申请日：2000-10-26

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： HSU LOUIS L C ,  WEINFURTNER OLIVER ,  WORDEMAN MATTHEW R

IPC: H02M3/07

CPC classification number: H02M3/073

Abstract: A charge pump generator system and method is provided in which on or more charge pumps are operated at multiple charging rates depending upon the level reached by a voltage supply. The system includes a limiter which provides a control signal based upon the level of the voltage supply. The control signal selects the frequency of a multiple frequency oscillator coupled thereto. The selected frequency determines the charge transfer rate of a charge pump used to maintain the voltage supply.

Abstract translation: 提供了一种电荷泵发电机系统和方法，其中根据电压达到的电平，多个充电速率的多个电荷泵运行。 该系统包括限幅器，其基于电压电平的电平提供控制信号。 控制信号选择与其耦合的多频振荡器的频率。 选定的频率决定了用于维持电压供应的电荷泵的电荷转移速率。

公开(公告)号：DE10196673T1

公开(公告)日：2003-08-28

申请号：DE10196673

申请日：2001-09-21

Applicant: IBM

Inventor： HSU LOUIS LU-CHEN ,  PARENT RICHARD MICHAEL ,  WORDEMAN MATTHEW R

IPC: G11C5/14 ,  G11C8/08 ,  G11C11/406 ,  G11C11/4074

Abstract: A system and method for considerable reduction of power consumption in memory circuits implementing Vbb (array body bias) and Vwl (negative word line) voltage generators. The system comprises switching off the negative WL generator during sleep or standby mode, so that no power is consumed. A relaxed refresh operation is carried out and the negative WL is powered by the Vbb generator. The noise coupled to the negative WL supply from BL swing is reduced due to the joint Vbb-Vwl decoupling scheme. In the active mode, the Vbb and Vneg are separated to avoid any cross-over noise and to maintain design flexibility. During power-on period, the ramp-up rate of Vbb level is improved by the Vwl generator. The advantages may be summarized as: (1) simpler Vbb generator design, (2) much smaller Vbb generator size, (3) reduced Vbb power, (4) no stand-by current from Vwl generator, (5) low decoupling noise for Vwl level during stand-by or sleep mode, (6) enhanced ramp-up rate for Vbb during power-on, (7) no cross-over noise between Vbb and Vwl during active mode, and (8) design flexibility of Vbb and Vwl in the active mode. The principles and advantages of the invention may be applied to any two or more DC generator systems, negative or positive.

公开(公告)号：MY117502A

公开(公告)日：2004-07-31

申请号：MYPI9802182

申请日：1998-05-15

Applicant: IBM

Inventor： JASO MARK A ,  MANDELMAN JACK A ,  TONTI WILLIAM R ,  WORDEMAN MATTHEW R

IPC: H01L27/01 ,  H01L21/00 ,  H01L21/20 ,  H01L21/76 ,  H01L21/762 ,  H01L21/84 ,  H01L27/12 ,  H01L31/0392

Abstract: A SEMICONDUCTOR DEVICE HAVING AREAS (100) THAT ARE SEMICONDUCTOR ON INSULATOR (SOI) AND AREAS (102) THAT ARE BULK, SINGLE CRYSTALLINE SEMICONDUCTIVE AREAS IS PROVIDED IN WHICH CONDUCTIVE SPACERS (105, 124) MAY BE FORMED TO ELECTRICALLY CONNECT THE SOI AREAS TO GROUND IN ORDER TO OVERCOME FLOATING BODY EFFECTS THAT CAN OCCUR WITH SOI. ADDITIONALLY, INSULATIVE SPACERS (107, 126) MAY BE FORMED ON THE SURFACE OF THE CONDUCTIVE SPACERS TO ELECTRICALLY ISOLATE THE SOI REGIONS (120) FROM THE BULK REGIONS (122). A NOVEL METHOD FOR MAKING BOTH OF THESE PRODUCTS IS PROVIDED IN WHICH THE EPITAXIALLY GROWN, SINGLE CRYSTALLINE BULK REGIONS NEED NOT BE SELECTIVELY GROWN, BECAUSE A SACRIFICIAL POLISHING LAYER IS DEPOSITED, IS ALSO PROVIDED.(FIG. 4)

公开(公告)号：DE10196673B4

公开(公告)日：2008-01-31

申请号：DE10196673

申请日：2001-09-21

Applicant: IBM

Inventor： HSU LOUIS LU-CHEN ,  PARENT RICHARD MICHAEL ,  WORDEMAN MATTHEW R

IPC: G11C8/08 ,  G11C5/14 ,  G11C11/406 ,  G11C11/4074

Abstract: A system and method for considerable reduction of power consumption in memory circuits implementing Vbb (array body bias) and Vwl (negative word line) voltage generators. The system comprises switching off the negative WL generator during sleep or standby mode, so that no power is consumed. A relaxed refresh operation is carried out and the negative WL is powered by the Vbb generator. The noise coupled to the negative WL supply from BL swing is reduced due to the joint Vbb-Vwl decoupling scheme. In the active mode, the Vbb and Vneg are separated to avoid any cross-over noise and to maintain design flexibility. During power-on period, the ramp-up rate of Vbb level is improved by the Vwl generator. The advantages may be summarized as: (1) simpler Vbb generator design, (2) much smaller Vbb generator size, (3) reduced Vbb power, (4) no stand-by current from Vwl generator, (5) low decoupling noise for Vwl level during stand-by or sleep mode, (6) enhanced ramp-up rate for Vbb during power-on, (7) no cross-over noise between Vbb and Vwl during active mode, and (8) design flexibility of Vbb and Vwl in the active mode. The principles and advantages of the invention may be applied to any two or more DC generator systems, negative or positive.

公开(公告)号：AU8990501A

公开(公告)日：2002-04-15

申请号：AU8990501

申请日：2001-09-21

Applicant: IBM

Inventor： PARENT RICHARD MICHAEL ,  WORDEMAN MATTHEW R

IPC: G11C5/14 ,  G11C8/08 ,  G11C11/406 ,  G11C11/4074

Abstract: A system and method for considerable reduction of power consumption in memory circuits implementing Vbb (array body bias) and Vwl (negative word line) voltage generators. The system comprises switching off the negative WL generator during sleep or standby mode, so that no power is consumed. A relaxed refresh operation is carried out and the negative WL is powered by the Vbb generator. The noise coupled to the negative WL supply from BL swing is reduced due to the joint Vbb-Vwl decoupling scheme. In the active mode, the Vbb and Vneg are separated to avoid any cross-over noise and to maintain design flexibility. During power-on period, the ramp-up rate of Vbb level is improved by the Vwl generator. The advantages may be summarized as: (1) simpler Vbb generator design, (2) much smaller Vbb generator size, (3) reduced Vbb power, (4) no stand-by current from Vwl generator, (5) low decoupling noise for Vwl level during stand-by or sleep mode, (6) enhanced ramp-up rate for Vbb during power-on, (7) no cross-over noise between Vbb and Vwl during active mode, and (8) design flexibility of Vbb and Vwl in the active mode. The principles and advantages of the invention may be applied to any two or more DC generator systems, negative or positive.