公开(公告)号：JPH0645554A

公开(公告)日：1994-02-18

申请号：JP5085693

申请日：1993-03-11

Applicant: IBM

Inventor： SAN HOO DON ,  JIYON CHIESUTAA MARINOFUSUKI

IPC: H01L27/04 ,  H01L21/3213 ,  H01L21/334 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

Abstract: PURPOSE: To provide a method for manufacturing a DRAM trench capacitor having a plurality of pillars in a trench. CONSTITUTION: A silicon oxide layer 12 is grown on a silicon substrate 10. A silicon nitride layer 14 and a silicon oxide layer 16 are bonded. Then, a polysilicon layer 18, a nitride layer 20 and a large-particle polysilicon layer 22 are adhered. thereafter, a trench is formed by a lithographic mask 24, and the large-particle polysilicon 22 is etched in CF4 . A surface-shape feature existing in the layer 22 is copied to the layer 20. In the case of conducting polysilicon etching with strong directivity, surface shape feature on the layer 20 is reinforced, transferred to the layer 18 with it as a mask, and the layers 16, 14, 12 are etched to form pillars.