公开(公告)号：JPH0661505A

公开(公告)日：1994-03-04

申请号：JP13064293

申请日：1993-06-01

Applicant: IBM

Inventor： KEBUIN KOKU CHIYAN ,  SAN HOO DON ,  DEIITAA POORU OIGEN KERUN ,  YANGU HOON RII

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792

Abstract: PURPOSE: To obtain a flash EEPROM which is operable at a low voltage and has a high resistance to the disturbance and a structure capable of scaling easily. CONSTITUTION: A flash EEPROM having MOS cells is manufactured. At each cell, programming and erase are made by the tunnel effect directed from a write gate 22 to a floating gate 22 and tunnel effect directed from the floating gate 14 to an erase gate 10. Directional dielectrics 16, 24 used are multilayer structure(MLS) oxides composed of thin oxide layers and thin polysilicon layers alternately laminated to form asymmetric layer structures; the uppermost or lowermost layer is thicker than others. In the result of this structure, the oxide shows a directionality i.e., the tunnel effect is easier in one direction than in the reverse direction. The oxides greatly enhance the tunnel effect (recognizable at a low voltage of 4.7 V).

公开(公告)号：JPH0684358A

公开(公告)日：1994-03-25

申请号：JP560493

申请日：1993-01-18

Applicant: IBM

Inventor： SAN HOO DON ,  KITAMURA TSUNEJI ,  KIRIHATA TOSHIAKI ,  SUNANAGA TOSHIO

IPC: G11C11/409 ,  G11C7/06 ,  G11C11/407 ,  G11C11/4091

Abstract: PURPOSE: To reduce the swing of a bit line by limiting the swing of a rise bit line to prescribed voltage higher than power voltage. CONSTITUTION: External voltages VCC and VSS are used for a word line driver 20, PMOS cell array 16 in an n-type well, a COMS AC connection sense amplifier 18 and a bit line monitor circuit 22. Since an initial bit line is precharged by VEQ which is larger than the threshold of QPCELL of VTP, a signal can be generated at high speed. A signal charge appearing on the bit line BL30 from an access cell is speedily detected in the sense amplifier at sense clocks ϕSR and ϕSP. Here, voltages VCC and VSS charge rise BL and discharge fall BL. Thus, sense speed improves. At that time, a reference bit is monitored in the monitor circuit 22, non-activates clocks ϕ1 and ϕ2 and limits voltage when it reaches setting voltage. Then, the swing of boosting voltage is limited between a power source and setting voltage and the swing of the bit line can be reduced.

公开(公告)号：JPH0645554A

公开(公告)日：1994-02-18

申请号：JP5085693

申请日：1993-03-11

Applicant: IBM

Inventor： SAN HOO DON ,  JIYON CHIESUTAA MARINOFUSUKI

IPC: H01L27/04 ,  H01L21/3213 ,  H01L21/334 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

Abstract: PURPOSE: To provide a method for manufacturing a DRAM trench capacitor having a plurality of pillars in a trench. CONSTITUTION: A silicon oxide layer 12 is grown on a silicon substrate 10. A silicon nitride layer 14 and a silicon oxide layer 16 are bonded. Then, a polysilicon layer 18, a nitride layer 20 and a large-particle polysilicon layer 22 are adhered. thereafter, a trench is formed by a lithographic mask 24, and the large-particle polysilicon 22 is etched in CF4 . A surface-shape feature existing in the layer 22 is copied to the layer 20. In the case of conducting polysilicon etching with strong directivity, surface shape feature on the layer 20 is reinforced, transferred to the layer 18 with it as a mask, and the layers 16, 14, 12 are etched to form pillars.

公开(公告)号：JPH06209090A

公开(公告)日：1994-07-26

申请号：JP24944591

申请日：1991-09-27

Applicant: IBM

Inventor： SAN HOO DON ,  UEI HAN ,  TAIRA YOICHI

IPC: G11C11/407 ,  G11C11/408 ,  H01L21/76 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H03K5/02

Abstract: PURPOSE: To minimize substrate effect in a PMOS transistor and to increase the width of the voltage swing of a word line in a word line driver circuit for DRAMs. CONSTITUTION: A separation trench 66 is provided around the N well of a PMOS transistor 58. A pulse generator circuit 52 is provided to give a certain potential to the transistor 58 so that a word line 60 can be shifted to a negative potential on activation. Also, a negative power supply circuit 54 is provided to give a lower potential to the N well when the pulse generator circuit 52 is started.

公开(公告)号：JPH06169565A

公开(公告)日：1994-06-14

申请号：JP35066891

申请日：1991-12-12

Applicant: IBM

Inventor： CHI RIAN CHIEN ,  SAN HOO DON ,  HIYUN JIYON SHIN

IPC: G11C11/407 ,  G05F1/56 ,  H02M3/07

Abstract: PURPOSE: To apply differential amplifiers to a small drop-out voltage regulator and improve power source elimination, by connecting a series regulating element with the outputs of the differential amplifiers, making a source-follower and constituting a booster of the differential amplifiers with voltage pump circuits. CONSTITUTION: A series regulating element MN1 connected with the outputs of differential amplifiers MN2-MN4 and MP1-MP2 acts as source-follower. A booster (booster VCC) INT of the differential amplifiers MN2-MN4 and MP1-MP2 is constituted of voltage pump circuits MP4-MP6, CRUMP1-CRUMP2, CSTORE. Gate potentials of the differential amplifiers MN2-MN4 and MP1-MP2 are increased with the voltage pump circuits MP4-MP6, CRUMP1-CRUMP2, CSTORE. Thereby, the differential amplifiers can be applied to a small drop-out voltage regulator, power source elimination can be improved, and lower external power source sensitivity can be obtained.

公开(公告)号：JPH05166375A

公开(公告)日：1993-07-02

申请号：JP8872592

申请日：1992-04-09

Applicant: IBM

Inventor： SAN HOO DON ,  YUN JIYON SHIN

IPC: G11C11/41 ,  G11C8/16 ,  G11C11/401

Abstract: PURPOSE: To obtain a memory cell, having a smallest silicon occupying area and high reliability by forming a double port memory by six transistors(TR) and providing a power source voltage line to supply a voltage at a prescribed intermediate level as well. CONSTITUTION: This memory cell is constituted of the six TRs of p-type TRs 28 and 34, controlled by word cables 44, 46 and p-type TRs 20, 24, 22 and 26 forming FF to be supplied with a power source voltage VC through a power source able 50. At the time of writing 1 in a port A in a state where a node X is 0, in advance to the writing, a voltage VC is dropped by not more than 50% to be the intermediate level. Then the conductive state of TR 24 is lowered by a node Y, to raise the potential of the node X. TR 26 comes into a double conductive state to further lower the potential of the node Y, and TR 24 becomes a non-conductive state to write data 1 by a stable flip operation. Similarly, using six TRs and high reliability using six TRs, asynchronous access is satisfactorily executed between ports A and B to make SAM of the smallest silicon area.

公开(公告)号：JPH04278285A

公开(公告)日：1992-10-02

申请号：JP32818191

申请日：1991-11-15

Applicant: IBM

Inventor： GARII BERA BURONAA ,  SAN HOO DON ,  UEI WANGU

IPC: G11C11/407 ,  G11C11/408 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

Abstract: PURPOSE: To shorten access time by driving a word line with a circuit maintaining the gate of an access transistor to negative potential through the use of DRAM using a word driving circuit reducing the word line to negative potential. CONSTITUTION: The voltage of the word line 10 is raised by using a constant negative voltage generation circuit 26 and a trench capacitor 25. Negative potential generated on a chip by the circuit 26 is stored in a capacitor 25 having capacitance which is considerably larger than that of the line 10. The word line driving circuit is constituted of an NMOS reducing transistor Tr24 and a PMOS raising Tr23. When negative potential is supplied to the source of 24, negative potential is supplied to the line 10 when Tr24 is gated to a conductive state since Tr is switched. Then, Tr23 is connected to the drain of Tr24 in series and the line 10 can be driven in a positive direction.

公开(公告)号：JPH03190426A

公开(公告)日：1991-08-20

申请号：JP31819090

申请日：1990-11-26

Applicant: IBM

Inventor： SAN HOO DON ,  CHII RIYAN CHIEN ,  YUN JIYON SHIN

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/07 ,  H03K17/04 ,  H03K17/567 ,  H03K19/08

Abstract: PURPOSE: To avoid a voltage drop between an emitter and a collector by using a horizontal bipolar transistor having a base defined by the gate of a polycrystalline silicon. CONSTITUTION: A horizontal gate-emphasized PNP transistor(TR) 31 is formed in a BiCMOS integrated circuit together with a longitudinal NPN TR. When an input 29 is a low level, the base connection of the TR 31 is gated by the operation of a P-channel device 33 and turned to a conductive state. At the time, the base device 31 conducts a current and holds a gate at low potential and voltage can be completely pulled up to a level Vdd. When the input state of an inverter is in a reverse state, a high level signal gates the device 34 at an on state, a collector is almost held at Vss and a P-channel device 32 connects its base and emitter together to turn the device to a non-conductive state. Consequently, the function of a MOS FET can be obtained and voltage drop between the collector and emitter can be avoided.