公开(公告)号：DE3586851T2

公开(公告)日：1993-06-09

申请号：DE3586851

申请日：1985-06-03

Applicant: IBM

Inventor： AICHELMANN JR ,  LANGE LAWRENCE KENNETH

IPC: G06F12/16 ,  G06F11/10 ,  H03M13/00

Abstract: An error correction code, especially suited for memory chips with multi-bit outputs, in which parity bits are calculated for each byte of the word and check bits are calculated for the word as a whole. In a 4-byte, 32-bit word, eight bits of error correction can correct up to four errors if the errors are restricted to corresponding bits in the 4 bytes.

公开(公告)号：DE3586851D1

公开(公告)日：1993-01-07

申请号：DE3586851

申请日：1985-06-03

Applicant: IBM

Inventor： AICHELMANN JR ,  LANGE LAWRENCE KENNETH

IPC: G06F12/16 ,  G06F11/10 ,  H03M13/00

Abstract: An error correction code, especially suited for memory chips with multi-bit outputs, in which parity bits are calculated for each byte of the word and check bits are calculated for the word as a whole. In a 4-byte, 32-bit word, eight bits of error correction can correct up to four errors if the errors are restricted to corresponding bits in the 4 bytes.

公开(公告)号：DE2329610A1

公开(公告)日：1974-01-10

申请号：DE2329610

申请日：1973-06-09

Applicant: IBM

Inventor： CHAO CHESTER CHIH-KUNG ,  LANGE LAWRENCE KENNETH ,  LINDBLOOM ERIC ,  SAVKAR ANIL DATTATRAYA

IPC: G06F11/22 ,  G01R31/28 ,  G01R31/3183 ,  G06F17/50 ,  H03K19/00 ,  G06F15/46