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    TESTABLE ARRAY LOGIC DEVICE
    1.
    发明专利
    TESTABLE ARRAY LOGIC DEVICE 未知

    公开(公告)号：DE3475460D1

    公开(公告)日：1989-01-05

    申请号：DE3475460

    申请日：1984-04-25

    Applicant: IBM

    Inventor： EICHELBERGER EDWARD BAXTER ,  LINDBLOOM ERIC

    IPC: G01R31/28 ,  H03K19/00 ,  H03K19/177

    Abstract: A PLA is constructed to improve random testing. Section circuits are provided that permit disabling sections of the output lines that are called segments so that the circuit can be tested one segment at a time. Selection circuits are also provided for enabling the product term lines only one at a time. Thus, while random test signals are conventionally applied to the PLA input terminals for test, only a small portion of the PLA is enabled for the test. Control signals for the selection circuits are generated randomly so that the portion of the PLA that is tested is varied randomly.

    WEIGHTED RANDOM PATTERN TESTING APPARATUS AND METHOD
    2.
    发明专利
    WEIGHTED RANDOM PATTERN TESTING APPARATUS AND METHOD 未知

    公开(公告)号：CA1241375A

    公开(公告)日：1988-08-30

    申请号：CA501737

    申请日：1986-02-12

    Applicant: IBM

    Inventor： EICHELBERGER EDWARD B ,  LANGMAID ROGER N ,  LINDBLOOM ERIC ,  MOTIKA FRANCO ,  SINCHAK JOHN L ,  WAICUKAUSKI JOHN A

    IPC: G02B13/04 ,  G01R31/28 ,  G02B13/06

    Abstract: Weighted Random Pattern Testing Apparatus and Method A method and apparatus for testing very large scale integrated circuit devices, most particularly Level Sensitive Scan Design (LSSD) devices, by applying differently configured sequences of pseudo-random patterns in parallel to each of the input terminals of the device under test, collecting the output responses from each of the output terminals in parallel, combining these outputs to obtain a signature which is a predetermined function of all of the sequences of parallel outputs and comparing the test signature with a known good signature obtained by computer simulation. The input test stimuli are further altered in a predetermined fashion as a function of the structure of the device to be tested, to individually weight the inputs in favor of more or less binary ones or zeros.

    5.
    发明专利
    未知

    公开(公告)号：DE2256135A1

    公开(公告)日：1973-06-20

    申请号：DE2256135

    申请日：1972-11-16

    Applicant: IBM

    Inventor： CARPENTER ROBERT GORDON ,  LINDBLOOM ERIC ,  MCMAHON JUN MAURICE THOMAS

    IPC: G01R31/28 ,  G01R31/3181 ,  G01R31/3183 ,  G06F11/22 ,  G01R31/26

    Abstract: A system for testing complex circuitry primarily in large scale integration where a great number of inputs and outputs must be tested and the internal circuitry is inaccessible. The test system has a weighted random number generator which applies a test signal to some input terminals of the logic under test more frequently than others. A particular input terminal to the logic under test can be accessed in proportion to the circuit switching activity associated with accessing that particular terminal.

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