公开(公告)号：EP1297652A4

公开(公告)日：2003-08-20

申请号：EP01932776

申请日：2001-04-30

Applicant: IBM

Inventor： LINDEMANN MARK ,  SMITH SEAN WILLIAM

IPC: G09C1/00 ,  H04L9/06 ,  H04L9/12 ,  G06F1/00

CPC classification number: H04L9/0625 ,  G09C1/00 ,  H04L2209/12

Abstract: A symmetric key cryptographic method is provided for short operations. The method includes batching a plurality of operation parameters (1503), and performing an operation according to a corresponding operation parameter (1505). The symmetric key cryptographic method is a Data Encryption Standard (DES) method. The short operations can be less than about 80 bytes. The short operations can be between 8 and 80 bytes. The method includes reading the batched parameters from a dynamic random access memory (1504), and transmitting each operation through a DES engine according to the operations parameter (1505).

公开(公告)号：DE60117255D1

公开(公告)日：2006-04-20

申请号：DE60117255

申请日：2001-04-30

Applicant: IBM

Inventor： LINDEMANN MARK ,  SMITH WILLIAM

IPC: G09C1/00 ,  H04L9/06 ,  G06F1/00 ,  H04L9/12

Abstract: A system for executing a symmetric key cryptographic method includes a processor selecting data paths, a key, an initialization vector, a memory storing batched operation parameters, a bus connected to the processor and the memory, a cryptographic processor connected to the bus and controlled by the processor for performing a plurality of operations according to the operations parameter, wherein data for each operation is received individually and separately from the batched operation parameters, wherein an output for each operation is transmitted separately, and a pair of first-in-first-out (FIFO) state machines controlled by the processor and selectably connected to one of the cryptographic processor and the bus, bypassing the cryptographic processor.

公开(公告)号：AT318032T

公开(公告)日：2006-03-15

申请号：AT01932776

申请日：2001-04-30

Applicant: IBM

Inventor： LINDEMANN MARK ,  SMITH SEAN WILLIAM

IPC: G09C1/00 ,  H04L9/06 ,  H04L9/12 ,  G06F1/00

Abstract: A system for executing a symmetric key cryptographic method includes a processor selecting data paths, a key, an initialization vector, a memory storing batched operation parameters, a bus connected to the processor and the memory, a cryptographic processor connected to the bus and controlled by the processor for performing a plurality of operations according to the operations parameter, wherein data for each operation is received individually and separately from the batched operation parameters, wherein an output for each operation is transmitted separately, and a pair of first-in-first-out (FIFO) state machines controlled by the processor and selectably connected to one of the cryptographic processor and the bus, bypassing the cryptographic processor.

公开(公告)号：DE60117255T2

公开(公告)日：2006-10-05

申请号：DE60117255

申请日：2001-04-30

Applicant: IBM

Inventor： LINDEMANN MARK ,  SMITH WILLIAM

IPC: G09C1/00 ,  H04L9/06 ,  G06F1/00 ,  H04L9/12

Abstract: A system for executing a symmetric key cryptographic method includes a processor selecting data paths, a key, an initialization vector, a memory storing batched operation parameters, a bus connected to the processor and the memory, a cryptographic processor connected to the bus and controlled by the processor for performing a plurality of operations according to the operations parameter, wherein data for each operation is received individually and separately from the batched operation parameters, wherein an output for each operation is transmitted separately, and a pair of first-in-first-out (FIFO) state machines controlled by the processor and selectably connected to one of the cryptographic processor and the bus, bypassing the cryptographic processor.

公开(公告)号：AU5927701A

公开(公告)日：2001-11-12

申请号：AU5927701

申请日：2001-04-30

Applicant: IBM

Inventor： LINDEMANN MARK ,  SMITH SEAN WILLIAM

IPC: G09C1/00 ,  H04L9/06 ,  H04L9/12

Abstract: A system for executing a symmetric key cryptographic method includes a processor selecting data paths, a key, an initialization vector, a memory storing batched operation parameters, a bus connected to the processor and the memory, a cryptographic processor connected to the bus and controlled by the processor for performing a plurality of operations according to the operations parameter, wherein data for each operation is received individually and separately from the batched operation parameters, wherein an output for each operation is transmitted separately, and a pair of first-in-first-out (FIFO) state machines controlled by the processor and selectably connected to one of the cryptographic processor and the bus, bypassing the cryptographic processor.