公开(公告)号：WO2004070773A3

公开(公告)日：2004-10-28

申请号：PCT/GB2004000434

申请日：2004-02-04

Applicant: IBM ,  IBM UK ,  BUFFET PATRICK ,  COHN JOHN ,  GROSSELFINGER KEVIN ,  LICHTENSTEIGER SUSAN ,  SMITH WILLIAM

Inventor： BUFFET PATRICK ,  COHN JOHN ,  GROSSELFINGER KEVIN ,  LICHTENSTEIGER SUSAN ,  SMITH WILLIAM

IPC: H01L20060101 ,  H01L27/00 ,  H01L27/02 ,  H01L27/118 ,  H03K19/00 ,  H03K19/173

CPC classification number: H01L27/11898 ,  H01L27/0207

Abstract: An integrated circuit structure has at least one voltage island and a pattern of power switches within the voltage island. The pattern determines the number of (and evenly spaces) the power switches according to the size of the serviceable area to which each of the power switches can provide power. The size of the power switches are matched to the current and voltage that will be provided by the power buses. The size of the serviceable area to which each of the power switches can provide power is dependent upon the size of the power switches.

Abstract translation: 集成电路结构在电压岛内具有至少一个电压岛和功率开关模式。 该模式根据每个电源开关可以提供电力的可用区域的大小确定电源开关的数量（并且均匀地间隔）。 电源开关的大小与电源总线提供的电流和电压相匹配。 每个电源开关可以提供电力的可服务区域的大小取决于电源开关的大小。

公开(公告)号：DE60117255D1

公开(公告)日：2006-04-20

申请号：DE60117255

申请日：2001-04-30

Applicant: IBM

Inventor： LINDEMANN MARK ,  SMITH WILLIAM

IPC: G09C1/00 ,  H04L9/06 ,  G06F1/00 ,  H04L9/12

Abstract: A system for executing a symmetric key cryptographic method includes a processor selecting data paths, a key, an initialization vector, a memory storing batched operation parameters, a bus connected to the processor and the memory, a cryptographic processor connected to the bus and controlled by the processor for performing a plurality of operations according to the operations parameter, wherein data for each operation is received individually and separately from the batched operation parameters, wherein an output for each operation is transmitted separately, and a pair of first-in-first-out (FIFO) state machines controlled by the processor and selectably connected to one of the cryptographic processor and the bus, bypassing the cryptographic processor.

公开(公告)号：AT509371T

公开(公告)日：2011-05-15

申请号：AT04707972

申请日：2004-02-04

Applicant: IBM

Inventor： BUFFET PATRICK ,  COHN JOHN ,  GROSSELFINGER KEVIN ,  LICHTENSTEIGER SUSAN ,  SMITH WILLIAM

IPC: H01L27/02 ,  H01L20060101 ,  H01L27/00 ,  H01L27/118 ,  H03K19/00 ,  H03K19/173

Abstract: An integrated circuit structure has at least one voltage island and a pattern of power switches within the voltage island. The pattern determines the number of (and evenly spaces) the power switches according to the size of the serviceable area to which each of the power switches can provide power. The size of the power switches are matched to the current and voltage that will be provided by the power buses. The size of the serviceable area to which each of the power switches can provide power is dependent upon the size of the power switches.

公开(公告)号：DE60117255T2

公开(公告)日：2006-10-05

申请号：DE60117255

申请日：2001-04-30

Applicant: IBM

Inventor： LINDEMANN MARK ,  SMITH WILLIAM

IPC: G09C1/00 ,  H04L9/06 ,  G06F1/00 ,  H04L9/12

Abstract: A system for executing a symmetric key cryptographic method includes a processor selecting data paths, a key, an initialization vector, a memory storing batched operation parameters, a bus connected to the processor and the memory, a cryptographic processor connected to the bus and controlled by the processor for performing a plurality of operations according to the operations parameter, wherein data for each operation is received individually and separately from the batched operation parameters, wherein an output for each operation is transmitted separately, and a pair of first-in-first-out (FIFO) state machines controlled by the processor and selectably connected to one of the cryptographic processor and the bus, bypassing the cryptographic processor.