公开(公告)号：DE3885185D1

公开(公告)日：1993-12-02

申请号：DE3885185

申请日：1988-06-16

Applicant: IBM

Inventor： HWANG WEI ,  LU CHAU-CHUN NICKY

IPC: H01L27/10 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108 ,  H01L29/78 ,  H01L21/82 ,  H01L21/205

Abstract: A new high density vertical trench transistor and trench capacitor DRAM (dynamic-random-access memory) cell is described incorporating a wafer with a semiconductor substrate (10) and an epitaxial layer (10) thereon including a vertical transistor (14) disposed in a shallow trench (100) stacked above and self-aligned with a capacitor in a deep trench (16). The stacked vertical transistor (4) has a channel partly on the horizontal surface and partly along the shallow trench sidewalls. The drain of the access transistor (14) is a lightly-doped drain structure (21) connected to a bitline element (22). The source (24) of the transistor, located at the bottom of the transistor trench (100) and on top of the center of the trench capacitor (16), is self-aligned and connected to polysilicon (28) contained inside the trench capacitor. Three sidewalls of the access transistor (14) are surrounded by thick oxide isolation (50) and the remaining one side is connected to drain and bitline contacts. The memory cell is located inside an n-well (26) and uses the n-well and heavily-doped substrate (10) as the capacitor counter-electrode plate. The cell storage node is the polysilicon (28) inside the trench capacitor. The fabrication method includes steps for growing epitaxial layers wherein an opening (100) is left which serves as the shallow trench access transistor region and provides self-alignment with the deep trench storage capacitor.