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    MAGNITUDE COMPARATOR
    1.
    发明申请
    MAGNITUDE COMPARATOR 审中-公开
    MAGNITUDE比较器

    公开(公告)号：WO2004040435A3

    公开(公告)日：2004-10-28

    申请号：PCT/GB0304610

    申请日：2003-10-24

    Applicant: IBM ,  IBM UK

    Inventor： HWANG WEI ,  WU KUN

    IPC: G06F7/02

    CPC classification number: G06F7/026

    Abstract: An apparatus and method for providing high speed computing power with efficient power consumption in a computing environment comprising a comparator with at least one input feed; a sign selector in electronic communication with the comparator; and result flag generator in electronic communication with both the sign selector and the comparator. The sign selector has input data feeds and an equivalent number of dedicated indicators for identifying signed numbers from unsigned numbers for each of the input data feeds. The result flag generator receives a first resultant feed from the comparator and a second resultant feed from the sign selector. The sign selector can be designed to provide a resultant output. The resultant output is generated after collective operations have been performed on the input feeds and selectively on other feeds such as a sign feed and an Ini feed.

    Abstract translation: 一种用于在包括具有至少一个输入馈送的比较器的计算环境中提供高效率功耗的高速计算能力的装置和方法; 与比较器进行电子通信的符号选择器; 和结果标志发生器与符号选择器和比较器进行电子通信。 符号选择器具有输入数据馈送和等效数量的专用指示符，用于从每个输入数据馈送的无符号数中识别有符号数字。 结果标志发生器从比较器接收第一个合成的馈送，并从标识选择器接收第二个合成的馈送。 符号选择器可以设计成提供合成输出。 在对输入馈送进行集体操作并选择性地在其他馈送（例如符号馈送和Ini馈送）上产生结果输出。

    DUAL TYPE THIN-FILM FIELD EFFECT TRANSISTOR AND APPLICATION EXAMPLE
    2.
    发明专利
    DUAL TYPE THIN-FILM FIELD EFFECT TRANSISTOR AND APPLICATION EXAMPLE 失效

    公开(公告)号：JP2001320058A

    公开(公告)日：2001-11-16

    申请号：JP2000139494

    申请日：2000-05-12

    Applicant: IBM

    Inventor： THOMAS DODERER ,  HWANG WEI ,  CHAN C TSUEI

    IPC: H01L21/764 ,  H01L29/786

    Abstract: PROBLEM TO BE SOLVED: To provide a method as well as a structure for a single device to perform both n-type conduction and p-type conduction. SOLUTION: An ultra-small electronic device includes a gate layer adapted to receive an input voltage. An insulating layer is formed on a gate layer while a conductive channel layer is formed on the insulating layer, and a current is carried between a source and a drain. The conductive channel layer is adapted to provide a dual channel. The dual channel comprises both a p-channel and an n-channel. One of the p-channel and the n-channel is selectively usable in response to the polarity of the input voltage. A method for forming the device and application example of the device is also disclosed and claimed.

    Magnitude comparator
    4.
    发明专利
    Magnitude comparator 未知

    公开(公告)号：AU2003278339A8

    公开(公告)日：2004-05-25

    申请号：AU2003278339

    申请日：2003-10-24

    Applicant: IBM

    Inventor： WU KUN ,  HWANG WEI

    IPC: G06F7/02

    Abstract: An apparatus and method for providing high speed computing power with efficient power consumption in a computing environment comprising a comparator with at least one input feed; a sign selector in electronic communication with the comparator; and result flag generator in electronic communication with both the sign selector and the comparator. The sign selector has input data feeds and an equivalent number of dedicated indicators for identifying signed numbers from unsigned numbers for each of the input data feeds. The result flag generator receives a first resultant feed from the comparator and a second resultant feed from the sign selector. The sign selector can be designed to provide a resultant output. The resultant output is generated after collective operations have been performed on the input feeds and selectively on other feeds such as a sign feed and an Ini feed.

    6.
    发明专利
    未知

    公开(公告)号：DE69126292T2

    公开(公告)日：1997-12-11

    申请号：DE69126292

    申请日：1991-10-28

    Applicant: IBM

    Inventor： DHONG SANG HOO ,  HWANG WEI ,  TAIRA YOICHI

    IPC: G11C11/407 ,  G11C11/408 ,  H01L21/76 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H03K5/02 ,  G11C8/00

    Abstract: A wordline driver circuit is shown for a DRAM, the circuit comprising a PMOS transistor structure (58) having one contact coupled to a wordline (60), a second contact coupled to a negative voltage supply and a gate coupled to a control input, the transistor having an N-well (64) about the gate, first and second contacts. An isolating structure (66) is positioned about the N-well (64) to enable it to be a separately controlled from surrounding N-well structures (64). Pulse circuits (52) are coupled to the transistor (58) for applying, when activated, a potential that enables the wordline (60) to transition to a more negative potential. A bias circuit is also provided for biasing the N-well (64) at a first potential and a second lower potential, the second lower potential applied when the pulse circuits (52) are activated. As a result, body effects in the PMOS transistor (58) are minimized while at the same time enabling a boost potential to be applied to the wordline (60).

    8.
    发明专利
    未知

    公开(公告)号：BR8803623A

    公开(公告)日：1989-02-08

    申请号：BR8803623

    申请日：1988-07-19

    Applicant: IBM

    Inventor： HWANG WEI ,  LU NICKY CHAU-CHU

    IPC: H01L27/04 ,  H01L21/334 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/94 ,  G11C11/34 ,  G11C11/21

    Abstract: A semiconductor memory cell structure incorporating a vertical access transistor over a trench storage capacitor including a semiconductor wafer having a semiconductor substrate (16) and an epitaxial layer (36) disposed thereon. A relatively deep polysilicon filled trench (26) is disposed in the epitaxial layer and substrate structure, the deep trench (26) having a composite oxide/nitride insulation layer (24) over its vertical and horizontal surfaces to provide a storage capacitor insulator. A relatively shallow trench is disposed in the epitaxial layer (36) over the deep trench (26) region, the shallow trench having an oxide insulation layer (46) on its vertical and horizontal surfaces thereof. A neck structure (34) of epitaxial polysilicon material extends from the top surface of the polysilicon filled deep trench (26) to the bottom surface of the shallow trench. Impurities are disposed in the epitaxial layer (36) on either side of the shallow trench to form semiconductor device drain (40) junctions and polysilicon material (48) is disposed in the shallow trench and over the epitaxial layer (36) to form semiconductor device transfer gate and wordline regions respectively.

    9.
    发明专利
    未知

    公开(公告)号：DE69220543T2

    公开(公告)日：1998-01-15

    申请号：DE69220543

    申请日：1992-04-11

    Applicant: IBM

    Inventor： BRONNER GARY B ,  DHONG SAN H ,  HWANG WEI

    IPC: H01L21/8242 ,  H01L21/76 ,  H01L27/10 ,  H01L27/108

    Abstract: Disclosed is a Dynamic Random Access Memory (DRAM) cell which includes a storage capacitor (28, 32, 34) disposed in a trench (28) formed in a semiconductor substrate (24, 30) and an access transistor (12) disposed in a well (18) which is opposite in conductivity type to that of the substrate (24, 30) and a buried oxide collar (36) which surrounds an upper portion of the trench (28).

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