公开(公告)号：WO02058330A3

公开(公告)日：2004-02-05

申请号：PCT/IB0200132

申请日：2002-01-14

Applicant: IBM ,  FURRER SIMEON ,  MAIWALD DIETRICH ,  SCHOTT WOLFGANG

Inventor： FURRER SIMEON ,  MAIWALD DIETRICH ,  SCHOTT WOLFGANG

IPC: H04L12/28 ,  G06F9/46 ,  G06F12/08 ,  H04L12/56

CPC classification number: H04W88/02 ,  H04W52/0229 ,  H04W84/10 ,  H04W84/18 ,  Y02D70/00 ,  Y02D70/144

Abstract: The invention provides a baseband system (8) for a short-range radio communication system. It is conform to the Bluetooth baseband specification and is well-suited for an efficient hardware implementation, providing a low-power, small-sized, and low-cost radio subsystem design. The baseband system comprises a transceiver unit (20) and a buffer unit (50), whereby the system has an efficient gate count and a reduced power consumption. The transceiver unit design is based on a pipelined signal processing with distributed data path flow control. The transceiver unit (20) processes outgoing and incoming packets, and comprises a plurality of signal processing units connected in sequence, whereby each signal processing unit is clocked by a common clock signal. A mode line is connected to each signal processing unit for switching each signal processing unit between a transmit mode and a receive mode. A control line to which each signal processing unit is connected communicates flow control information either in the transmit mode to one or more of the preceding signal processing units or in the receive mode to one or more of the following signal processing units. The buffer unit (50) comprises a buffer system that applies a flexible memory organization concept, which leads to an efficient implementation of buffers or storage elements in terms of gate count and power consumption, and offers the flexibility to dynamically allocate memory for variable length user packets.

Abstract translation: 本发明提供了一种用于短距离无线电通信系统的基带系统（8）。 它符合蓝牙基带规范，非常适合高效的硬件实现，提供低功耗，小尺寸和低成本的无线电子系统设计。 基带系统包括收发器单元（20）和缓冲单元（50），由此该系统具有有效的门数和降低的功耗。 收发器单元设计基于具有分布式数据路径流量控制的流水线信号处理。 收发器单元（20）处理输出和输入分组，并且包括顺序连接的多个信号处理单元，由此每个信号处理单元由公共时钟信号计时。 模式线连接到每个信号处理单元，用于在发送模式和接收模式之间切换每个信号处理单元。 每个信号处理单元所连接的控制线将发送模式中的流量控制信息传送到前述信号处理单元中的一个或多个或接收模式中的一个或多个信号处理单元。 缓冲单元（50）包括缓冲系统，其应用灵活的存储器组织概念，其导致在门计数和功耗方面有效地实现缓冲器或存储元件，并且提供了灵活性以动态地为可变长度用户分配存储器 数据包。

公开(公告)号：DE69314356T2

公开(公告)日：1998-03-26

申请号：DE69314356

申请日：1993-06-14

Applicant: IBM

Inventor： CHEVILLAT PIERRE ,  ELEFTHERIOU EVANGELOS ,  MAIWALD DIETRICH

IPC: G11B20/14 ,  G11B5/09 ,  G11B20/10 ,  H04L25/03 ,  H04L25/497

Abstract: PCT No. PCT/EP93/01500 Sec. 371 Date Jul. 20, 1995 Sec. 102(e) Date Jul. 20, 1995 PCT Filed Jun. 14, 1993 PCT Pub. No. WO94/29989 PCT Pub. Date Dec. 22, 1994The present application makes use of a novel adaptive noise-predictive partial-response equalization scheme for channels (30) exhibiting spectral nulls and/or near nulls. The noise-predictive partial-response (PR) equalizer employed in the different embodiments of the present invention consists of a linear PR equalizer (32) which shapes the channel response to a predetermined partial-response function, followed by a linear predictor. This scheme modifies the output sequence of said linear partial-response equalizer (32) by whitening the total distortion, i.e. by whitening the noise components and the residual interference components at said linear PR equalizer output, thereby achieving the best possible signal-to-noise ratio (SNR) before detection.

公开(公告)号：DE69314356D1

公开(公告)日：1997-11-06

申请号：DE69314356

申请日：1993-06-14

Applicant: IBM

Inventor： CHEVILLAT PIERRE ,  ELEFTHERIOU EVANGELOS ,  MAIWALD DIETRICH

IPC: G11B20/14 ,  G11B5/09 ,  G11B20/10 ,  H04L25/03 ,  H04L25/497

Abstract: PCT No. PCT/EP93/01500 Sec. 371 Date Jul. 20, 1995 Sec. 102(e) Date Jul. 20, 1995 PCT Filed Jun. 14, 1993 PCT Pub. No. WO94/29989 PCT Pub. Date Dec. 22, 1994The present application makes use of a novel adaptive noise-predictive partial-response equalization scheme for channels (30) exhibiting spectral nulls and/or near nulls. The noise-predictive partial-response (PR) equalizer employed in the different embodiments of the present invention consists of a linear PR equalizer (32) which shapes the channel response to a predetermined partial-response function, followed by a linear predictor. This scheme modifies the output sequence of said linear partial-response equalizer (32) by whitening the total distortion, i.e. by whitening the noise components and the residual interference components at said linear PR equalizer output, thereby achieving the best possible signal-to-noise ratio (SNR) before detection.

公开(公告)号：BR0206547A

公开(公告)日：2004-03-02

申请号：BR0206547

申请日：2002-01-14

Applicant: IBM

Inventor： FURRER SIMEON ,  MAIWALD DIETRICH ,  SCHOTT WOLFGANG

IPC: H04L12/28

Abstract: Communication device for processing outgoing and incoming packets. The device includes a plurality of signal processing units connected in sequence, each signal processing unit being clocked by a common clock signal. The device further includes a mode line connected to each signal processing unit for switching each signal processing unit between a transmit mode and a receive mode. The device further includes a control line to which each signal processing unit is connected. The control line communicating flow control information either in the transmit mode to at least one of the preceding signal processing units or in the receive mode to at least one of the following signal processing units.

公开(公告)号：AU2002219440A1

公开(公告)日：2002-07-30

申请号：AU2002219440

申请日：2002-01-14

Applicant: IBM

Inventor： MAIWALD DIETRICH ,  FURRER SIMEON ,  SCHOTT WOLFGANG

IPC: H04L12/28 ,  G06F12/08 ,  H04L12/56 ,  G06F9/46

Abstract: Communication device for processing outgoing and incoming packets. The device includes a plurality of signal processing units connected in sequence, each signal processing unit being clocked by a common clock signal. The device further includes a mode line connected to each signal processing unit for switching each signal processing unit between a transmit mode and a receive mode. The device further includes a control line to which each signal processing unit is connected. The control line communicating flow control information either in the transmit mode to at least one of the preceding signal processing units or in the receive mode to at least one of the following signal processing units.

公开(公告)号：CA2431134C

公开(公告)日：2007-07-03

申请号：CA2431134

申请日：2002-01-14

Applicant: IBM

Inventor： MAIWALD DIETRICH ,  FURRER SIMEON ,  SCHOTT WOLFGANG

IPC: H04L12/28 ,  H04L12/56 ,  H04L29/02

Abstract: The invention provides a baseband system for a short-range radio communicati on system. It is conform to the Bluetooth baseband specification and is well- suited for an efficient hardware implementation, providing a low-power, smal l- sized, and low-cost radio subsystem design. The baseband system comprises a transceiver unit and a buffer unit, whereby the system has an efficient gate count and a reduced power consumption. The transceiver unit design is based on a pipelined signal processing with distributed data path flow control. The transceiver unit processes outgoing and incoming packets, and comprises a plurality of signal processing units connected in sequence, whereby each signal processing unit is clocked by a common clock signal. A mode line is connected to each signal processing unit for switching each signal processin g unit between a transmit mode and a receive mode. A control line to which eac h signal processing unit is connected communicates flow control information either in the transmit mode to one or more of the preceding signal processin g units or in the receive mode to one or more of the following signal processi ng units. The buffer unit comprises a buffer system that applies a flexible memory organization concept, which leads to an efficient implementation of buffers or storage elements in terms of gate count and power consumption, an d offers the flexibility to dynamically allocate memory for variable length us er packets. The buffer system for storing data of the first processing unit and second processing unit comprises a plurality of storage elements, whereby ea ch storage element has a first storage unit and a second storage units. A switc h subsystem is provided for switching each storage element between first and second modes. In the first mode each first storage unit is addressable by th e first processing unit and each second storage unit is addressable by the second processing unit. In the second mode each second storage unit is addressable by the first processing unit and each first storage unit is addressable by the second processing unit.

公开(公告)号：CA2431134A1

公开(公告)日：2002-07-25

申请号：CA2431134

申请日：2002-01-14

Applicant: IBM

Inventor： SCHOTT WOLFGANG ,  FURRER SIMEON ,  MAIWALD DIETRICH

IPC: H04L12/28

Abstract: The invention provides a baseband system for a short-range radio communicati on system. It is conform to the Bluetooth baseband specification and is well- suited for an efficient hardware implementation, providing a low-power, smal l- sized, and low-cost radio subsystem design. The baseband system comprises a transceiver unit and a buffer unit, whereby the system has an efficient gate count and a reduced power consumption. The transceiver unit design is based on a pipelined signal processing with distributed data path flow control. The transceiver unit processes outgoing and incoming packets, and comprises a plurality of signal processing units connected in sequence, whereby each signal processing unit is clocked by a common clock signal. A mode line is connected to each signal processing unit for switching each signal processin g unit between a transmit mode and a receive mode. A control line to which eac h signal processing unit is connected communicates flow control information either in the transmit mode to one or more of the preceding signal processin g units or in the receive mode to one or more of the following signal processi ng units. The buffer unit comprises a buffer system that applies a flexible memory organization concept, which leads to an efficient implementation of buffers or storage elements in terms of gate count and power consumption, an d offers the flexibility to dynamically allocate memory for variable length us er packets. The buffer system for storing data of the first processing unit and second processing unit comprises a plurality of storage elements, whereby ea ch storage element has a first storage unit and a second storage units. A switc h subsystem is provided for switching each storage element between first and second modes. In the first mode each first storage unit is addressable by th e first processing unit and each second storage unit is addressable by the second processing unit. In the second mode each second storage unit is addressable by the first processing unit and each first storage unit is addressable by the second processing unit.

公开(公告)号：AT158911T

公开(公告)日：1997-10-15

申请号：AT93912969

申请日：1993-06-14

Applicant: IBM

Inventor： CHEVILLAT PIERRE ,  ELEFTHERIOU EVANGELOS ,  MAIWALD DIETRICH

IPC: G11B20/10 ,  H04L25/03 ,  H04L25/497

公开(公告)号：BRPI0206547B1

公开(公告)日：2015-11-10

申请号：BR0206547

申请日：2002-01-14

Applicant: IBM

Inventor： MAIWALD DIETRICH ,  FURRER SIMEON ,  SCHOTT WOLFGANG

IPC: H04L12/28

Abstract: "sistema de banda base digital"'. a invenção proporciona um sistema de banda base para um sistema de radiocomunicação de curto alcance. ele está de acordo com a especificação de banda base bluetooth e é bem adequado para uma implementação eficiente de hardware, proporcionando um projeto de subsistema de rádio de baixa potência, pequeno porte e baixo custo. o sistema de banda base compreende uma unidade transceptora e uma unidade de armazenamento temporária, pelo que o sistema tem uma contagem de portas eficiente e um consumo de energia reduzido. o projeto da unidade transceptora está baseado em um processamento de sinal por encadeamento com controle de fluxo de rotas de dados distribuídos. a unidade transceptora processa pacotes de saída e de chegada e compreende uma pluralidade de unidades processadoras de sinais conectadas em seqüência, pelo que cada unidade processadora de sinais é cronometrada por um sinal de relógio comum. uma linha de modo é conectada a cada unidade processadora de sinais para comutar cada unidade processadora de sinais entre um modo de transmissão e um modo de recepção. uma linha de controle à qual cada unidade processadora de sinais é conectada comunica informação de controle de fluxo no modo de transmissão para uma ou mais das unidades processadoras de sinais precedentes ou no modo de recepção para uma ou mais das unidades processadoras de sinais seguintes. a unidade de armazenamento temporário compreende um sistema de armazenamento temporário que aplica um conceito de organização de memória flexível, que leva a uma implementação eficiente de elementos de armazenamentos temporários ou de armazenamento em termos de contagem de portas e consumo de energia e oferece a flexibilidade para alocar memória dinamicamente para pacotes de usuário de comprimento variável. o sistema de armazenamento temporário para armazenar dados da primeira unidade de processamento e da segunda unidade de processamento compreende uma pluralidade de elementos de armazenamento, pelo que cada elemento de armazenamento tem uma primeira unidade de armazenamento e uma segunda unidade de armazenamento. um subsistema de comutação é proporcionado para comutar cada elemento de armazenamento entre os primeiro e segundo modos. no primeiro modo, cada primeira unidade de armazenamento é endereçável pela primeira unidade de processamento e cada segunda unidade de armazenamento é endereçável pela segunda unidade de processamento. no segundo modo, cada segunda unidade de armazenamento é endereçável pela primeira unidade de processamento e cada primeira unidade de armazenamento é endereçável pela segunda unidade de processamento.

公开(公告)号：DE60226454D1

公开(公告)日：2008-06-19

申请号：DE60226454

申请日：2002-01-14

Applicant: IBM

Inventor： FURRER SIMEON ,  MAIWALD DIETRICH ,  SCHOTT WOLFGANG

IPC: H04L12/28

Abstract: Communication device for processing outgoing and incoming packets. The device includes a plurality of signal processing units connected in sequence, each signal processing unit being clocked by a common clock signal. The device further includes a mode line connected to each signal processing unit for switching each signal processing unit between a transmit mode and a receive mode. The device further includes a control line to which each signal processing unit is connected. The control line communicating flow control information either in the transmit mode to at least one of the preceding signal processing units or in the receive mode to at least one of the following signal processing units.