ADAPTIVE ASYNCHRONOUS EQUALIZATION USING LEAKAGE
    1.
    发明申请
    ADAPTIVE ASYNCHRONOUS EQUALIZATION USING LEAKAGE 审中-公开
    使用泄漏的自适应异步均衡

    公开(公告)号:WO2007051693A3

    公开(公告)日:2007-06-28

    申请号:PCT/EP2006067340

    申请日:2006-10-12

    Abstract: An apparatus, system, and method are disclosed for adaptive asynchronous equalization using leakage. An equalizer sums products of a plurality of tap signals from a delay line sampling a read signal and a plurality of corresponding tap coefficients to form an equalized signal in an asynchronous time domain having a first sampling rate. A leaky function module calculates a leaky function for each tap coefficient in the asynchronous time domain. An adaptation module adapts each of the tap coefficients as the leaky function for each tap coefficient summed with a signal-dependent updating function for each tap coefficient.

    Abstract translation: 公开了一种使用泄漏进行自适应异步均衡的装置,系统和方法。 均衡器对来自对读取信号进行采样的延迟线和多个对应抽头系数的多个抽头信号的乘积进行求和,以在具有第一采样率的异步时域中形成均衡的信号。 泄漏功能模块计算异步时域中每个抽头系数的泄漏函数。 适配模块将每个抽头系数适配为每个抽头系数的泄漏函数,用于针对每个抽头系数的与信号相关的更新函数相加。

    DATA OVERWRITING IN PROBE BASE DATA STORAGE DEVICE

    公开(公告)号:JP2004005969A

    公开(公告)日:2004-01-08

    申请号:JP2003133291

    申请日:2003-05-12

    Applicant: IBM

    Abstract: PROBLEM TO BE SOLVED: To provide a method for overwriting data in a probe base data storage device wherein the data are represented by the existence/absence of a pit formed on a storage surface by a device probe. SOLUTION: Input data are encoded such that continuous bits of first values in coded input data are divided by at least one bit of another value. Overwritten data bits v 0 , v 1 , ... are generated from the coded input data b 0 , b 1 , ... used to overwrite data on the storage surface 4. The overwritten data bits are formula 1 with respect to i ≥1 when a pit represents the first value in the data storage device, and are generated such that v 0 has the first value. The overwritten data bits are v 1 = b i-1 with respect to i ≥1 and are generated such that v 0 has another value. COPYRIGHT: (C)2004,JPO

    Write-erase endurance lifetime of memory storage devices

    公开(公告)号:GB2483194A

    公开(公告)日:2012-02-29

    申请号:GB201121003

    申请日:2010-07-26

    Applicant: IBM

    Abstract: A memory management system and method for managing memory blocks of a memory device of a computer. The system includes a free block data structure (12) including free memory blocks (14) for writing, and sorting the free memory blocks in a predetermined order based on block write-erase endurance cycle count and receiving new user-write requests to update existing data and relocation write requests to relocate existing data separately, a user-write block pool (IS) for receiving youngest blocks holding user-write data (i.e., any page being updated frequently) from the free block data structure, a relocation block pool (20) for receiving oldest blocks holding relocation data (i.e., any page being updated infrequently) from the free block data structure, and a garbage collection pool structure (24) for selecting at least one of user-write blocks and relocation blocks for garbage collection, wherein the selected block is moved back to the free block data structure upon being relocated and erased.

    METHOD AND APPARATUS FOR MULTIUSER-INTERFERENCE REDUCTION

    公开(公告)号:CA2179979C

    公开(公告)日:2001-07-03

    申请号:CA2179979

    申请日:1994-02-10

    Applicant: IBM

    Abstract: The present invention concerns an apparatus and method for reducing the multiuser-interference of input signals. The apparatus in accordance with th e present invention comprises a multivariate predictor (81) and a decision quantizer (82), said multivariate predictor (81) operating on interference signals '(D) provided by means for extracting interference signals (83), said interference signals '(D) being obtained from said input signals and output signals b(D) which are available at an output of said decision quantizer (82) and fed back from there to said means for extracting interference signals (83).

    8.
    发明专利
    未知

    公开(公告)号:DE68915274T2

    公开(公告)日:1994-11-10

    申请号:DE68915274

    申请日:1989-07-12

    Applicant: IBM

    Abstract: In a data transmission wherein a transmitting modem transmits data signals to a receiving modem via a telephone line, the process of the invention consists in rotating (12), in the transmitting modem, the phase of the point of the constellation resulting from a group of data bits by a predetermined phase value, and then rotating (22) after, a predetermined delay in the receiving modem, the phase of the estimated point resulting from the transformation of the analog signal, by the opposite of said predetermined phase value, the mean-square error between the rotated point and the estimated point of the constellation being used to determine whether the receiving modem is out of synchronization or not.

    Dynamisch eingestellter Schwellenwert zum Belegen eines sekundären Cache-Speichers

    公开(公告)号:DE112012004209T5

    公开(公告)日:2014-09-11

    申请号:DE112012004209

    申请日:2012-10-19

    Applicant: IBM

    Abstract: Das Belegen mit Daten, die in einen sekundären Cache-Speicher eines Datenspeichers eingegeben werden sollen, wird gesteuert durch Ermitteln einer Vergleichsmaßzahl potenzieller Daten, Einstellen eines Schwellenwerts der Vergleichsmaßzahl; Zurückweisen potenzieller Daten, die dem sekundären Cache-Speicher des Datenspeichers bereitgestellt werden, deren Vergleichsmaßzahl kleiner ist als der Schwellenwert; und Aufnehmen potenzieller Daten, deren Vergleichsmaßzahl gleich dem Schwellenwert oder größer als dieser ist. Die Einstellung des Schwellenwerts der Vergleichsmaßzahl wird ermittelt durch Vergleichen einer Referenzmaßzahl in Bezug auf Treffer von Daten, die in den sekundären Cache-Speicher des Datenspeichers zuletzt eingegeben wurden, mit einer Referenzmaßzahl in Bezug auf Treffer bei Daten, die aus dem sekundären Cache-Speicher des Datenspeichers verlagert wurden; Verringern des Schwellenwerts, wenn die Referenzmaßzahl der zuletzt eingegebenen Daten größer ist als die Referenzmaßzahl der zuletzt verlagerten Daten; und Vergrößern des Schwellenwerts, wenn die Referenzmaßzahl der zuletzt eingegebenen Daten kleiner ist als die Referenzmaßzahl der zuletzt verlagerten Daten.

    Promotion of partial data segments in flash cache

    公开(公告)号:GB2509289A

    公开(公告)日:2014-06-25

    申请号:GB201406779

    申请日:2012-08-30

    Applicant: IBM

    Abstract: Exemplary method, system, and computer program product embodiments for efficient track destage in secondary storage in a more effective manner, are provided. In one embodiment, by way of example only, for temporal bits employed with sequential bits for controlling the timing for destaging the track in a primary storage, the temporal bits and sequential bits are transferred from the primary storage to the secondary storage. The temporal bits are allowed to age on the secondary storage. Additional system and computer program product embodiments are disclosed and provide related advantages.

Patent Agency Ranking