公开(公告)号：GB2520991A

公开(公告)日：2015-06-10

申请号：GB201321579

申请日：2013-12-06

Applicant: IBM

Inventor： ZOELLIN CHRISTIAN ,  MEADING NICOLAS

IPC: G01R31/3185

Abstract: An integrated circuit chip comprises at least two integrated circuits IC1, IC2, at least three scan chains SC1, SC2, SC3 and multiplexor circuitry M1, M2, M3, MC_IN, MC_OUT. Each integrated circuit (IC) comprises an input port and an output port. The scan chains (SC) and the ICs are coupled by default in a series chain having alternating ICs and scan chains. Each scan chain comprises a first SC input port coupled by default with the IC output port of the adjacent IC. Each scan chain comprises a first SC output port coupled by default with the IC input port of the adjacent IC. In a bypass mode, the multiplexor circuitry is arranged to bypass a first portion of the series chain such that the IC output port of the IC adjacent to the first bypassed scan chain is coupled to the first SC input port of the scan chain adjacent to the last bypassed IC; and to bypass a second portion of the series chain such that the IC input port of the IC adjacent to the last bypassed scan chain is coupled with the first SC output of the scan chain adjacent to the first bypassed IC.