公开(公告)号：JPH11260936A

公开(公告)日：1999-09-24

申请号：JP1651299

申请日：1999-01-26

Applicant: IBM

Inventor： NOWAK EDWARD J ,  MIN HOO TON

IPC: H01L21/8234 ,  H01L21/8236 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a series of field-effect transistors(FETs), each of which has the gate oxide layer of a single thickness on a silicon wafer but is driven by different operating voltage. SOLUTION: A plysilicon gate layer is formed on a gate dielectric layer (oxide) 138 on a silicon wafer. During the period when an ordinary NFET 120 and a PFET 124 are formed, the determined position of a high-voltage FET is shielded. After the formation of the ordinary FET, the shield of the high-voltage FET is removed. Recommendably, the dopant of boron (B) or phosphorus (P) is injected into a gate and a source/drain region with a specified concentration and a specified energy. As a result, the gate and the source/drain region is depleted. An effective gate dielectric layer 136, which is thicker than the ordinary NFET 120 and PFET 124, is obtained.

公开(公告)号：JPH11260909A

公开(公告)日：1999-09-24

申请号：JP1713999

申请日：1999-01-26

Applicant: IBM

Inventor： NOWAK EDWARD J ,  MIN HOO TON

IPC: H01L21/76 ,  H01L21/822 ,  H01L27/02 ,  H01L27/04 ,  H01L27/088 ,  H01L27/12

Abstract: PROBLEM TO BE SOLVED: To realize a decoupling capacitance permitted by a semiconductor device by forming a high junction capacitance while forming an implantation layer under an insulating layer of a first circuit region, and connecting the implantation layer to wells of a second circuit region. SOLUTION: An isolation oxide layer 22, a first device layer 24, an isolation layer 20, and a first polarity type highly doped implantated layer 25 that is formed under the layer 22 are formed at a first circuit region of an SOI structure. Further, a second circuit region (e.g. a bulk device region) is adjacent to the first circuit region, and has a bulk region 30, first polarity type wells 32 and 34, a second device region having regions 36, 38 and 42, a region 44 of first and second polarity type, the layer 20 and the like. Both circuit regions are located on a second polarity type substrate 50. The first circuit region covers almost the whole chip. If a larger capacitance is required, a second polarity type dopant 40 is used under the layer 25 formed by ion implantation with 1 MeV energy.