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公开(公告)号：DE2723706A1
公开(公告)日：1978-01-05
申请号：DE2723706
申请日：1977-05-26
Applicant: IBM
Abstract: 1535670 Data processing INTERNATIONAL BUSINESS MACHINE CORP 1 June 1977 [30 June 1976] 23243/77 Heading G4A In a data processing system comprising (control) storage 6 which is organized in page frames 0-63 at least some of which are for relocatable pages, a match between a set target (virtual) address 22 and a currently active (real) address in storage 6 is detected (specifically for diagnostic purposes) by means of a word address comparator 28 and an individual latch (in a register 60) for each page frame in the relocatable area of storage 6. A particular latch is set (when address matching is called for) when the page part of the target address is matched by the (virtual) page address currently allocated to the associated page frame, and a complete match is detected, 15, when a word address match is signalled by the comparator 28 concurrently with accessing of that particular page frame. Matching of the page addresses of relocatable pages is performed by the normal processor facilities under microprogram control to avoid the use of an expensive and slow special purpose comparator. In the case of address matching being required in resident (non- relocatable) storage, the page address comparison is performed by a page address comparator 24 which is of lesser width (corresponding to the number of page frames 0-55 of resident storage) than the width required for page address comparison for relocatable pages. Non-resident page frames 56-63 are assigned to different programs which are run in sequential time slices 1-8. A diagnostic program may be temporarily or permanently assigned time slice 8. Accessing of each particular relocatable page frame is signalled by a time slice control 12. When a page is entered in a relocatable page frame 56-63 its full address is loaded into a special store (80), Fig. 2 (not shown), having a location for each time slice (except possibly time slice 8). The target address is also loaded into local storage for time slice 8, and the program assigned this time slice is arranged to effect the sequential comparison of the page addresses in the different time slice locations of the special store with the target address from the time slice 8 local storage.
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公开(公告)号：DE2831261A1
公开(公告)日：1979-02-01
申请号：DE2831261
申请日：1978-07-15
Applicant: IBM
Inventor： MITCHELL JUN MATTHEW JOSEPH , PAGE HOWARD LOOMIS
Abstract: A high performance channel-to-channel adapter for interconnecting two or more digital computers or digital data processors. Multiple input/output device addresses are recognized by the channel-to-channel adapter. The channel-to-channel adapter makes the proper processor-to-processor connection by matching device addresses. In particular, it interconnects for data transfer purposes the two processors for which the same device address has been received. The assignment of device addresses for processor use and the direction of data transfer are by conventions agreed to among the software systems executing on the interconnected processors. The channel-to-channel adapter does not have a view of these conventions. In the more general case, two device addresses are assigned by software convention to each processor-to-processor link, one address being used to transfer data in one direction and the other address being used to transfer data in the opposite direction.
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