SYNCHRONIZING CHANNEL-TO-CHANNEL ADAPTER

    公开(公告)号:AU3555778A

    公开(公告)日:1979-11-01

    申请号:AU3555778

    申请日:1978-04-28

    Applicant: IBM

    Abstract: A high performance channel-to-channel adapter for interconnecting two or more digital computers or digital data processors. Multiple input/output device addresses are recognized by the channel-to-channel adapter. The channel-to-channel adapter makes the proper processor-to-processor connection by matching device addresses. In particular, it interconnects for data transfer purposes the two processors for which the same device address has been received. The assignment of device addresses for processor use and the direction of data transfer are by conventions agreed to among the software systems executing on the interconnected processors. The channel-to-channel adapter does not have a view of these conventions. In the more general case, two device addresses are assigned by software convention to each processor-to-processor link, one address being used to transfer data in one direction and the other address being used to transfer data in the opposite direction.

    2.
    发明专利
    未知

    公开(公告)号:DE2831261A1

    公开(公告)日:1979-02-01

    申请号:DE2831261

    申请日:1978-07-15

    Applicant: IBM

    Abstract: A high performance channel-to-channel adapter for interconnecting two or more digital computers or digital data processors. Multiple input/output device addresses are recognized by the channel-to-channel adapter. The channel-to-channel adapter makes the proper processor-to-processor connection by matching device addresses. In particular, it interconnects for data transfer purposes the two processors for which the same device address has been received. The assignment of device addresses for processor use and the direction of data transfer are by conventions agreed to among the software systems executing on the interconnected processors. The channel-to-channel adapter does not have a view of these conventions. In the more general case, two device addresses are assigned by software convention to each processor-to-processor link, one address being used to transfer data in one direction and the other address being used to transfer data in the opposite direction.

    DATA PROCESSING APPARATUS WITH INTERSEGMENT CALL

    公开(公告)号:DE3275668D1

    公开(公告)日:1987-04-16

    申请号:DE3275668

    申请日:1982-07-23

    Applicant: IBM

    Abstract: A computer architecture is disclosed which permits Intersegment program calls with associated selective allocation of data segments of varying lengths. The calling program controls selective allocation of segments to the called program either from its own allocated segments or, under its control, fresh segments can be generated but the called program can be used to control the lengths of the segments being allocated. In this way, recursive calls to the same program cannot affect the function or data or other programs or of the same program in a previous call. Also allocation of data segments can be postponed until execution resulting in more flexible execution of programs written without knowledge of the details of other co-executing programs.

Patent Agency Ranking