公开(公告)号：GB2511314A

公开(公告)日：2014-09-03

申请号：GB201303464

申请日：2013-02-27

Applicant: IBM

Inventor： TRONG SON DAO ,  MULLER SILVIA MELITTA ,  KLEIN MICHAEL ,  LAYER CHRISTOPHE

IPC: G06F7/483

Abstract: Disclosed is a method of operating a fast fused-multiply-add pipeline in a floating point unit of a processor, using a plurality of operands 32, 34, 90 as an input. A data formatting step is performed after a partial product reduction in the pipeline instead of conversion of the input operands 32, 34, 90 to an internal floating point format. The method may comprise the steps of receiving a first and second input operands to be multiplied together, receiving a third operand to be added to the result of the multiplication. The multiplication is performed in a multiplier block to give partial product results, which are input into a carry-save adder block. Next a partial product reduction is performed on the partial product results to generate a carry-save result comprising a sum term and a carry term. Then a data formatting step is carried out on the carry-save result and a carry-out bit is generated. Finally the result is generated by adding the carry-save result to the third operand.