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    Residue calculation in modulo system using 4:2 counter
    1.
    发明专利
    Residue calculation in modulo system using 4:2 counter 未知

    公开(公告)号：GB2456406A

    公开(公告)日：2009-07-22

    申请号：GB0822762

    申请日：2008-12-15

    Applicant: IBM

    Inventor： GERWIG GUENTER ,  FLEISCHER BRUCE MARTIN ,  HAESS JUERGEN ,  TRONG SON DAO ,  SCHWARZ ERIC MARK ,  WETTER HOLGER

    IPC: G06F7/72

    Abstract: A residue of an operand with a width of n bits with respect to a modulo m where m=2b-1, can be calculated by partitioning the operand into segments, each of b bits starting with the Least Significant Bit (LSB). The segments are applied to a counter reduction tree (21) comprising levels (22, 23) of adders (24) The adders (24) of a first level (22) below an operand register (25) with successive registers keeping the successive bit positions of the operand are 4:2 counters (24) having four inputs (In1, In2, In3, In4) plus a propagate input (44), a carry and a sum output (45, 46) plus a propagate output (43) each. the first level (22) are grouped in fours, such that the propagate outputs (43) are ring like connected with the propagate inputs (44), and that the first to fourth inputs (In1, In2, In3, In4) of the counters (24) are connected with successive registers of said operand register (25) such that first inputs (In4) of the counters (24) are connected with four successive registers in ascending order followed by second (In3), third (In2) and fourth inputs (In1), wherein a decoding is performed only one time at the end of the counter tree (21) and thus at the end of the residue generation process. This leads to a reduction in the area needed on the chip to make the calculation, relaxes the timing requirement, as the calculation requires fewer logical levels, and increases the error detection rate for a single random type of operation.

    Method for executing a load instruction in a pipeline processor, putting the data in the target address into a buffer then loading the requested data.
    2.
    发明专利
    Method for executing a load instruction in a pipeline processor, putting the data in the target address into a buffer then loading the requested data. 未知

    公开(公告)号：GB2454816A

    公开(公告)日：2009-05-20

    申请号：GB0822115

    申请日：2008-12-04

    Applicant: IBM

    Inventor： TRONG SON DAO ,  HAESS JUERGEN ,  HUTTON DAVID SHANE ,  KLEIN MICHAEL ,  RELL JOHN GILBERT JR ,  SCHWARZ ERIC MARK ,  SHUM KEVIN CHUNG-LUNG

    IPC: G06F9/312 ,  G06F9/38

    Abstract: Disclosed is a method and system for operating the execution unit of a computer, the execution unit having a pipeline-based execution flow during which load instructions are processed. The load instructions having the function of loading data from a storage means into a predetermined location within the pipeline, preferably a register-implemented pipeline. The method has the steps of, when a load instruction occurs in the pipeline, reading (610) the current value of the target location, and buffering (620) the current target value at a predetermined location within said pipeline. Next, the value of the source location is loaded (610) and stored (620) at the target location, the pipeline is executed according to its execution flow, using the loaded value for computing purposes. If an event (630) indicating that the loaded value is not correct occurs, (660) the buffered original value may be used instead of the loaded value. The execution unit may be a floating point unit with the reading and/or loading of the data being done using a multiply-add data path.

    Fast fused-multiply-add pipeline
    4.
    发明专利
    Fast fused-multiply-add pipeline 未知

    公开(公告)号：GB2511314A

    公开(公告)日：2014-09-03

    申请号：GB201303464

    申请日：2013-02-27

    Applicant: IBM

    Inventor： TRONG SON DAO ,  MULLER SILVIA MELITTA ,  KLEIN MICHAEL ,  LAYER CHRISTOPHE

    IPC: G06F7/483

    Abstract: Disclosed is a method of operating a fast fused-multiply-add pipeline in a floating point unit of a processor, using a plurality of operands 32, 34, 90 as an input. A data formatting step is performed after a partial product reduction in the pipeline instead of conversion of the input operands 32, 34, 90 to an internal floating point format. The method may comprise the steps of receiving a first and second input operands to be multiplied together, receiving a third operand to be added to the result of the multiplication. The multiplication is performed in a multiplier block to give partial product results, which are input into a carry-save adder block. Next a partial product reduction is performed on the partial product results to generate a carry-save result comprising a sum term and a carry term. Then a data formatting step is carried out on the carry-save result and a carry-out bit is generated. Finally the result is generated by adding the carry-save result to the third operand.

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