公开(公告)号：JP2000152129A

公开(公告)日：2000-05-30

申请号：JP31468698

申请日：1998-11-05

Applicant: IBM

Inventor： NAKANO MASASHI

IPC: G09G3/36 ,  G09G3/20 ,  G09G5/00 ,  G09G5/37 ,  H03M7/14 ,  H04N5/66

Abstract: PROBLEM TO BE SOLVED: To reduce the quantity of data which are changed during the transfer of them by converting a 1st image data part included in the image data into those which are more similar to a 2nd image data of a type different from the 1st image data part in the binary number representation that is divided into blocks in every finite bit number and restoring the converted 1st image data part into its original state after transferring them. SOLUTION: It's supposed that the image data include many image data parts (a) 0000 and (b) 1111. When the entire image data are processed (addition of +1) via an adder 300 before the image data are transferred via a data line 400, the image data parts (a) 0000 and (b) 1111 are turned into (a) 0001 and (b) 0000 respectively. Thereby the number of transited image data is reduced down to 1 (after processing) from largest 4 (before processing). These two types of image data parts, i.e., 0001 and 0000 to be compared with each other become similar to each other when they are processed.

公开(公告)号：JP2000148605A

公开(公告)日：2000-05-30

申请号：JP31468198

申请日：1998-11-05

Applicant: IBM

Inventor： YAMASHITA HIROSHI ,  NAKANO MASASHI

IPC: G06F13/38 ,  G06F13/00 ,  G06F13/42 ,  G09G3/20 ,  G09G3/36

Abstract: PROBLEM TO BE SOLVED: To effectively decrease quantity of data variation by a relatively small scale additional circuit by specifying data lines divisionally by blocks, obtaining a redundant control signal from whether or not the majority decision result of data transition in a block has priority, and using it as inversion information. SOLUTION: A D-FF(data flip-flop circuit or data latching circuit) 102 latches input data. Then EX-OR(exclusive OR) 104 compares it with the last data to make a 36-bit MAJORITY(majority decision) 106. The decision result is EX- ORed 108 with the last Invert signal and a D-FF(data flip-flop circuit or data latch circuit) 110 times the result to the data of the D-FF 102, EX-ORs 112 it with the 36-bit data, and inverts the data according to the Invert. The processed (inverted) data can be restored by subjecting them to EX-OR 114 with the Invert.