公开(公告)号：JP2002366346A

公开(公告)日：2002-12-20

申请号：JP2001168737

申请日：2001-06-04

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： KOBAYASHI YOSHINAO ,  NAMURA TAKESHI ,  KATO KENYA

IPC: G06F7/487 ,  G06F7/38 ,  G06F7/508 ,  G06F7/552 ,  G06F7/52

CPC classification number: G06F7/552 ,  G06F7/483

Abstract: PROBLEM TO BE SOLVED: To reduce the number of computing elements constituting a square multiplier for floating-point numbers and also to increase the processing speed by circuit techniques for an arithmetic unit. SOLUTION: The square multiplier for floating-point numbers is provided with a false carry generation circuit 21a which falsely generates information related to carry of prescribed bits in the arithmetic of a variable as an arithmetic object, an MSB(Most Significant Bit) look-ahead circuit 21b which decides the MSB in the arithmetic result in advance from the variable as the arithmetic object, and a combinational circuit which uses information related to carry, which is generated by the false carry generation circuit 21a, to perform arithmetic of the variable while performing rounding processing based on the position of the MSB decided by the MSB look-ahead circuit 21b.

Abstract translation: 要解决的问题：为了减少构成浮点数的平方乘法器的计算元件的数量，并且还通过用于算术单元的电路技术来提高处理速度。 解决方案：浮点数的平方乘法器设置有错误携带产生电路21a，其在作为运算对象的变量的算术中错误地生成与规定位的进位相关的信息，MSB（最高有效位）先行 电路21b，从运算对象的变量中预先算出运算结果中的MSB，以及组合电路，使用由假携带发生电路21a生成的与携带有关的信息，进行变量的运算，同时执行 基于由MSB预先电路21b决定的MSB的位置的舍入处理。

公开(公告)号：JP2007218808A

公开(公告)日：2007-08-30

申请号：JP2006041535

申请日：2006-02-17

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： SEIKE SANAE ,  NAMURA TAKESHI ,  YOKOTA TOSHIHIKO

IPC: G01R31/28 ,  G06F11/22 ,  H01L21/822 ,  H01L27/04

CPC classification number: G01R31/31725 ,  G01R31/31726 ,  G01R31/318594

Abstract: PROBLEM TO BE SOLVED: To enable a receiving scan latch to release original data, even if the arrival times for the release/capture clocks differ in each clock domain, in data transfer between clock domains. SOLUTION: A plurality of clock domains to each of which a testing clock is supplied from a separate clock generation circuit are provided. In each clock domain, scan latch on the border of the clock domains for receiving an input from another clock domain includes a master latch 30 for latching the input in response to a first clock; a slave latch 32 for latching an output from the master latch in response to a second clock; a selector 34 for supplying a scan input to the master latch, when a mode switchover signal is at a first level and supplying a system input to the master latch, when the signal is at a second level; and a clock control circuit 36 for turning off the first clock, when the mode switchover signal transits from the first level to the second level. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：即使时钟域之间的数据传输，即使每个时钟域的释放/捕获时钟的到达时间不同，为了使接收扫描锁存器释放原始数据。 提供了从单独的时钟产生电路提供测试时钟的多个时钟域。 在每个时钟域中，用于从另一个时钟域接收输入的时钟域的边界上的扫描锁存器包括用于响应于第一时钟锁存输入的主锁存器30; 从锁存器32，用于响应于第二时钟锁存来自主锁存器的输出; 当信号处于第二电平时，当模式切换信号处于第一电平并将系统输入提供给主锁存器时，选择器34用于向主锁存器提供扫描输入; 以及时钟控制电路36，用于当模式切换信号从第一电平转换到第二电平时关闭第一时钟。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2001306532A

公开(公告)日：2001-11-02

申请号：JP2000118588

申请日：2000-04-19

Applicant: IBM

Inventor： TANAKA NOBUYASU ,  NAMURA TAKESHI

IPC: G06F15/16 ,  G06F3/00 ,  G06F5/10 ,  G06F9/38 ,  G06F15/167 ,  G06F15/177 ,  G06F15/80 ,  G06T1/20

Abstract: PROBLEM TO BE SOLVED: To provide an information processor, for which it is not necessary to analyze the number of stages of FIFO from the character of data for improving performance, by dynamically having the number of stages of FIFO optimal at that time. SOLUTION: This device is provided with a data FIFO 22 for storing data sets and a next pointer 29 having storage areas as many as in this data FIFO. The preceding data set is stored in a storage area '1' of the data FIFO 22 and the following data set is stored in a storage area '7' of the data FIFO 22. At this time, '7' is stored in the storage area '1' of the next pointer 29 as storage area information of following data. On the basis of this storage area information '7', the following data set is read out of the storage area '7' of the data FIFO 22.