公开(公告)号：JP2010258532A

公开(公告)日：2010-11-11

申请号：JP2009103213

申请日：2009-04-21

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： TAKEMURA KIYOSHI ,  TANAKA NOBUYASU ,  OKADA TADAYUKI ,  OGAWA MAKOTO

IPC: H03M7/40

CPC classification number: H03M7/42

Abstract: PROBLEM TO BE SOLVED: To shorten the processing time of conversion from a plurality of bit lengths, allocated to a plurality of character strings, respectively, to a plurality of codes.
SOLUTION: A Huffman table decoding circuit stores a bit length bl[N] assigned to each character on input of the bit length assigned to the character, and stores the order of respective character strings among character strings to which the same bit length is assigned in code_fin[N]. Further, the number of characters to which the same bit length is assigned is stored in bl_count[M], and on the basis of the storage, a minimum code having the same bit length is stored in code_min[M]. Consequently, a selector 31 extracts the minimum code specified with bl[N] among a plurality of minimum standards stored in the code_min[N], and an adding circuit 32 performs processing for adding the minimum code to the value stored in code_fin[N] in parallel, and defines the added results as a code assigned to the character.
COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：将分配给多个字符串的多个位长度的转换处理时间分别缩短为多个代码。 解决方案：霍夫曼表解码电路存储在分配给字符的比特长度的输入上分配给每个字符的比特长度bl [N]，并且存储相同字符串在相同比特长度 在code_fin [N]中分配。 此外，分配相同位长的字符数存储在bl_count [M]中，并且基于存储，具有相同位长的最小代码被存储在code_min [M]中。 因此，选择器31提取存储在code_min [N]中的多个最小标准中用bl [N]指定的最小代码，并且加法电路32执行将最小代码加到存储在code_fin [N]中的值的处理， 并行，并将添加的结果定义为分配给角色的代码。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2003044310A

公开(公告)日：2003-02-14

申请号：JP2001208998

申请日：2001-07-10

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： KAJITA TSUNEHIRO ,  OGURA AKIHIRO ,  NISHIDA MITSUHIRO ,  TAKEUCHI ATSUYA ,  TANAKA NOBUYASU ,  ITO HIROSHI

IPC: G06F1/32 ,  G06F11/20 ,  G06F13/00 ,  G06F15/177

Abstract: PROBLEM TO BE SOLVED: To provide a clustering system with improved processing efficiency by eliminating, transfer of management data for fail over among the respective server machines. SOLUTION: The respective server machines 11 to 14 are provided with management data storage parts 60 to 61 to store the management data of processings to be executed in the server machines, batteries 70 to 73 to supply power to interface parts 50 to 53 to electrically and mechanically connect at least the management data storage parts 60 to 61 and the server machines with a communication line 110 when a fault occurs in the server machines, the interface parts 50 to 53 to receive power supply by a battery in the first server machine transfer the management data read from the management data storage parts 60 to 61 to a second server machine and continues service to a client based on the management data received by the second server machine when the fault occurs in a first server machine among the respective server machines.

Abstract translation: 要解决的问题：通过消除在各个服务器机器之间转移用于故障转移的管理数据来提供具有改进的处理效率的集群系统。 解决方案：相应的服务器机器11至14设置有管理数据存储部件60至61，用于存储要在服务器机器中执行的处理的管理数据，电池70至73，以向接口部件50至53供电以电和 当服务器机器发生故障时，至少将管理数据存储部件60至61与服务器机器连接至通信线路110，由第一服务器机器中的电池接收电力的接口部件50至53将 管理数据从管理数据存储部分60至61读取到第二服务器机器，并且当在各个服务器机器中的第一服务器机器中发生故障时，基于由第二服务器机器接收的管理数据，继续向客户端服务。

公开(公告)号：JP2003044268A

公开(公告)日：2003-02-14

申请号：JP2001213054

申请日：2001-07-13

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： TANAKA NOBUYASU

IPC: G06F7/50 ,  G06F7/506

Abstract: PROBLEM TO BE SOLVED: To provide a carry output circuit suppressing delay time without complicating the circuit even when the number of input digits increases.
SOLUTION: The carry output circuit is provided with a low-order digit carry part 151 computing the low-order digit values of respective numerical values A and B and outputting low-order carry signals, a pertinent digit all 1 detection part 152 detecting that the respective OR output values of the pertinent addition digits of the respective numerical values A and B are all 1, a pertinent digit AND output part 44a outputting a first temporary pertinent carry signal to the arithmetic part of highorder digits when input is present from both of the low-order digit carry part 151 and the pertinent digit all 1 detection part 152, a pertinent digit carry part 153 computing the respective values of the pertinent addition digits of the respective numerical values A and B and outputting a second temporary pertinent carry signal to the arithmetic part of the high-order digits and a pertinent digit OR output part 44b outputting pertinent carry signals to the arithmetic part of the high-order digits when at least one of the first temporary pertinent carry signal from the pertinent digit AND output part 44a and the second temporary pertinent carry signal from the pertinent digit carry part 153 is inputted.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：即使当输入数字数量增加时，也提供抑制延迟时间而不使电路复杂化的进位输出电路。 解决方案：进位输出电路设有低位数进位部分151，计算各数值A和B的低位数值并输出低位进位信号，相关数字全1检测部分152检测到 各个数值A和B的相关加法位数的相应OR输出值全部为1，相应的数字AND输出部分44a输入第一临时相关进位信号到高位数字的运算部分 低位数进位部分151和相关数字全1检测部分152，相关数字进位部分153计算相应数值A和B的相关相加数字的相应值，并输出第二临时相关进位信号到 高位数字的算术部分和相关的数字或输出部分44b将相关进位信号输出到高位数字的运算部分 当输入来自相关数字AND输出部分44a的第一临时相关进位信号和来自相关数位进位部分153的第二临时相关进位信号中的至少一个时，

公开(公告)号：JP2009169897A

公开(公告)日：2009-07-30

申请号：JP2008010263

申请日：2008-01-21

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DOJI HIROSHI ,  MAKIMURA HIRONORI ,  KIDA MINORU ,  TANAKA NOBUYASU

IPC: G06F12/16

CPC classification number: G11C29/56 ,  G11C2029/0401 ,  G11C2029/2602

Abstract: PROBLEM TO BE SOLVED: To provide a method or the like capable of shortening the execution time and starting time of a test more when a multi-processor system performs a test of a main memory more than when one processor performs the test. SOLUTION: The method for testing a main memory (MM) by a multi-processor system (MPS) provided with a main processor (MP) and a plurality of sub-processors (SP) having a DMA transfer mechanism and a local store (LS) is provided, which has the steps: in which the MP allocates a partial memory area (PMA) of the MM to each SP; for requesting each SP for a test of a PMA; in each SP files data in its LS in response to the request; in which each SP performs DMA transfer of data of the LS to a PMA; in which each SP performs DMA transfer of the data of the PMA to the LS; in which each SP tests the LS; and the MP integrates test results in response to each test completion to determine the test results of the MM. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供一种当多处理器系统比一个处理器执行测试时更多地执行主存储器的测试，能够更多地缩短执行时间和测试的开始时间的方法等。 解决方案：通过具有主处理器（MP）的多处理器系统（MPS）和具有DMA传送机制和本地的多个子处理器（SP）来测试主存储器（MM）的方法 存储（LS），其具有以下步骤：其中MP向每个SP分配MM的部分存储区域（PMA）; 要求每个SP进行PMA测试; 在每个SP文件中的数据在其LS中响应请求; 其中每个SP执行LS的数据到PMA的DMA传输; 其中每个SP执行将PMA的数据DMA传送到LS; 其中每个SP测试LS; 并且MP将测试结果与每个测试完成相结合以确定MM的测试结果。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2004013313A

公开(公告)日：2004-01-15

申请号：JP2002163020

申请日：2002-06-04

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： TANAKA NOBUYASU ,  NISHINO KIYOSHI ,  OGURA AKIHIRO

IPC: G06F12/08 ,  G06F3/06 ,  G06F12/00 ,  G11B20/10 ,  G11B20/12

CPC classification number: G06F3/0659 ,  G06F3/0613 ,  G06F3/0689 ,  G06F12/0866 ,  G11B20/1217

Abstract: PROBLEM TO BE SOLVED: To provide a storage device and a system, a method, and a program for information processing which can shorten a formatting time and also shorten the recording time of data.
SOLUTION: The storage device includes at least one storage medium 40, a storage means 32 of storing format data of a plurality of patterns corresponding to the patterns, a means 34 of receiving a sector address for specifying a sector of the storage medium 40 to be written to and a pattern identifier for specifying the pattern of format data to be written to the storage medium 40, and a means 36 of reading the format data of the pattern corresponding to the pattern identifier out of the storage means 32 and writing the read-out format data to the sector of the storage medium 40 corresponding to the received sector address.
COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2003150415A

公开(公告)日：2003-05-23

申请号：JP2001339706

申请日：2001-11-05

Applicant: IBM

Inventor： TANAKA NOBUYASU ,  OGURA AKIHIRO ,  TAKEUCHI ATSUYA

IPC: G06F3/06 ,  G06F12/00 ,  G11B20/10

Abstract: PROBLEM TO BE SOLVED: To provide an external storage device provided with a plurality of recording mediums and features of these recording mediums. SOLUTION: This external storage device 110 is provided with a semiconductor memory 200, a hard disk 210 having slower access speed than the semiconductor memory 200, a determination part 275 for determining whether write data can be stored in the semiconductor memory 200 or not when receiving write access for indicating writing of data for the external storage device 110, and an access processing part 277 which compresses write data and stores it in the semiconductor memory 200 when it is determined that the write data can be stored in the semiconductor memory 200 and stores the write data in the hard disk 210 when it is determined that the write data cannot be stored in the semiconductor memory 200. The external storage device 110 has a storage region having large storage capacity when compared with storage capacity of the semiconductor memory 200.

公开(公告)号：JP2001306532A

公开(公告)日：2001-11-02

申请号：JP2000118588

申请日：2000-04-19

Applicant: IBM

Inventor： TANAKA NOBUYASU ,  NAMURA TAKESHI

IPC: G06F15/16 ,  G06F3/00 ,  G06F5/10 ,  G06F9/38 ,  G06F15/167 ,  G06F15/177 ,  G06F15/80 ,  G06T1/20

Abstract: PROBLEM TO BE SOLVED: To provide an information processor, for which it is not necessary to analyze the number of stages of FIFO from the character of data for improving performance, by dynamically having the number of stages of FIFO optimal at that time. SOLUTION: This device is provided with a data FIFO 22 for storing data sets and a next pointer 29 having storage areas as many as in this data FIFO. The preceding data set is stored in a storage area '1' of the data FIFO 22 and the following data set is stored in a storage area '7' of the data FIFO 22. At this time, '7' is stored in the storage area '1' of the next pointer 29 as storage area information of following data. On the basis of this storage area information '7', the following data set is read out of the storage area '7' of the data FIFO 22.

公开(公告)号：JPH07114358A

公开(公告)日：1995-05-02

申请号：JP25184893

申请日：1993-10-07

Applicant: IBM

Inventor： OGURA AKIHIRO ,  TANAKA NOBUYASU

IPC: G09G3/36 ,  G09G3/20 ,  G09G3/28

Abstract: PURPOSE: To display a halftone without generating any flicker or moving phenomenon. CONSTITUTION: In a unit area 32 of a 1st frame F3n of LCD, picture elements containing the colors (surrounded by circles) of different lightness in the order of RGB in column direction are displayed in the order of RGB in row direction and in the unit area 32 of 2nd and 3rd frames F3n+1 and F3n+2 , the picture elements are displayed according to this order in the row and column directions as well. Concerning the respective picture elements in the unit area 32, the pictures containing the colors of different lightness in the order of RGB are displayed in the order of the 1st, 2nd and 3rd frames F3n , F3n+1 and F3n+2 . Thus, the lightness of only one of three colors RGB is changed for each picture element, the lightness is equally changed inside the unit area, the respective colors are distributed to the different positions of respective frames, and the colors of different lightness are equally arranged without concentrating the picture elements of different lightness into one frame.

公开(公告)号：JPH0793569A

公开(公告)日：1995-04-07

申请号：JP21726293

申请日：1993-09-01

Applicant: IBM

Inventor： TANAKA NOBUYASU ,  MORI MASAYA ,  TAKAYANAGI KAZUNORI

IPC: G09G5/20 ,  G06T11/20

Abstract: PURPOSE: To plot the straight line and circular arc of a width at a high speed on a graphic display. CONSTITUTION: For both of a point for which only an X coordinate is increased by one from a present point and the point for which only a Y coordinate is increased by one, whether or not they are present between contour lines f1 and f2 for stipulating the line of width 1 is judged. When the point for which only the X coordinate is increased by one is present between the contour lines f1 and f2, the point is plotted and selected as the next pixel. When it is not so and the point for which only the Y coordinate is increased by one is present between the contour lines f1 and f2, the point is plotted and selected as the next pixel. When neither of them is present between the contour lines f1 and f2, the point for which both X coordinate and Y coordinate are increased by one is plotted and selected as the next pixel.

公开(公告)号：JP2010268146A

公开(公告)日：2010-11-25

申请号：JP2009116851

申请日：2009-05-13

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： TANAKA NOBUYASU ,  NISHINO KIYOSHI ,  TAKEMURA KIYOSHI

IPC: H03M7/40 ,  G06F17/30

CPC classification number: G11C15/00 ,  H03M7/3084

Abstract: PROBLEM TO BE SOLVED: To increase possibility that a location where data have been written lately can be selected from a plurality of locations where data are stored. SOLUTION: When a signal MATCH representing a plurality of addresses with specific character data in an associative memory cell array 26 stored therein is input, whether at least a portion of the plurality of addresses exist in a low address region is determined by a latch 90, an AND circuit 92 and an OR circuit 94; by the latch 90, a NOT circuit 96, a NAND circuit 98 and an AND circuit 100, a signal MATCH from an high address region is masked when at least a portion of the plurality of addresses exist in the low address region; and a priority encoder 102 outputs, as an address to be selected out of the plurality of addresses, the largest address out of the addresses represented by the signal MATCH inputted without being masked. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：可以从存储数据的多个位置中选择最近写入数据的位置的可能性。 解决方案：当输入表示存储在其中的相关存储单元阵列26中具有特定字符数据的多个地址的信号MATCH时，是否存在多个地址中的至少一部分存在于低地址区域中 锁存器90，AND电路92和OR电路94; 通过锁存器90，NOT电路96，NAND电路98和AND电路100，当低地址区域中存在多个地址的至少一部分时，屏蔽来自高地址区域的信号MATCH; 并且优先级编码器102作为从多个地址中选择的地址输出由不被屏蔽输入的信号MATCH所表示的地址中的最大地址。 版权所有（C）2011，JPO＆INPIT