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    5.
    发明专利
    未知

    公开(公告)号：DE1255719B

    公开(公告)日：1967-12-07

    申请号：DEJ0021978

    申请日：1962-06-22

    Applicant: IBM

    Inventor： PENOYER RALPH F

    IPC: H03B19/16 ,  H03K3/47 ,  H03K19/10

    Abstract: 992,920. Tunnel diode logic and oscillating circuits. INTERNATIONAL BUSINESS MACHINES CORPORATION. June 27, 1962 [June 29, 1961], No. 24601/62. Heading H3T. In a tunnel diode phase logic circuit comprising a first and second stage, each stage having at least one resonant circuit comprising a tunnel diode in series with an inductor, a periodically varying signal is produced in the inductor of the or each resonant circuit of the first stage by means of an A.C. external source so that a sustained oscillation can be produced in that resonant circuit when the tunnel diode is operated in the negative resistance region of its characteristic, and the output signal derived from the oscillations in the or each resonant circuit of the first stage is applied to the inductor of the resonant circuit of the second stage so that sustained oscillations can be produced in the resonant circuit of the second stage when its tunnel diode is operated in the negative resistance region of its characteristic. As shown in Fig. 1, the logical circuit comprises three stages 10, 11, 12, stage 10 comprising three resonant circuits 13, 14, 15 and stages 11, 12 each having one resonant circuit 16, 17 respectively. The resonant circuits are constructed similarly and oscillate at a frequency f 0 when the tunnel diodes are biased into the negative resistance regions of their respective characteristics by means of clock pulses V A , V B , Vc. Input windings 13E and 14E of resonant circuits 13, 14 are coupled with an input signal V D of frequency f 0 and input winding 15 E is coupled to an input signal V E of frequency f 0 but 180 degrees out of phase with respect to the input signal V D . During the applications of clock pulse V A to the first stage and also input signals V D and V E resonant circuits 13, 14, 15 oscillate at a frequency f 0 but with phase dependent upon the input signal to produce output signals in windings 16E, 16G, 16H of the transformer 16 of a second stage 11. Before clock pulse V A is terminated clock pulse V B is applied to terminal 16I to bias the diode 16A into its negative resistance region of its characteristic so that the resonant circuit 16 of this stage will oscillate at a frequency f 0 and with a phase dependent upon the majority of the phases of the signals VF, VG, VH. An output signal VI is taken from the stage 11 and coupled to a third stage 12 by means of input winding 17E. Before clock pulse VB is terminated clock pulse VC is applied to the tunnel diode 17A of this last stage, so that the circuit 17 oscillates at frequency f 0 and with the same phase as signal VI. However, due to the direction of output winding 17F the output signal V 0 is 180 degrees out of phase with VI, i.e. the last stage 12 acts as an invertor. By considering the phase of signal VD as binary 1 and that of signal VE as binary 0 logical AND, OR and INVERTOR circuits can be built up. In the embodiment of Fig. 6 the circuit comprises a pair of stages defined by resonant circuits 50, 51 each having a tunnel diode 52, 52 1 connected in series with an inductor 53, 53 1 , clock pulses VA, VB being applied to the tunnel diodes sequentially. A reference signal VR and an input signal VD are supplied to node 56 and during the application of clockpulse VA the output signal VF is taken via conductor 60 and resistor 61 to node 56 1 of the second stage to which node reference signal VR and input signals VG, VH are also applied. Resonant circuit 51 oscillates when the tunnel diode is biased into its negative resistance region and the phase of the output signal V 0 is determined by the majority of the phases of the input signals. In both the circuits of Figs. 1 and 6 the reference signal VR serves as a means for preventing cumulative phase shifts when the information signal is transferred from one stage to the next.

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