公开(公告)号：GB2597884B

公开(公告)日：2022-06-22

申请号：GB202116692

申请日：2020-04-02

Applicant: IBM

Inventor： RALF WINKELMANN ,  MICHAEL FEE ,  MATTHIAS KLEIN ,  CARSTEN OTTE ,  EDWARD CHENCINSKI ,  HANNO EICHELBERGER

IPC: G06F9/52 ,  G06F11/30 ,  G06F12/08 ,  G06F13/16

Abstract: The present disclosure relates to a method for a computer system comprising a plurality of processor cores, wherein a cached data item is assigned to a first core of the processor cores for exclusively executing an atomic primitive by the first core. The method comprises, while the execution of the atomic primitive is not completed by the first core, receiving from a second core at a cache controller a request for accessing the data item. In response to determining that a second request of the data item is received from a third core, of the plurality of processor cores, before receiving the request of the second core, a rejection message may be returned to the second core.

公开(公告)号：GB2532232A

公开(公告)日：2016-05-18

申请号：GB201420116

申请日：2014-11-12

Applicant: IBM

Inventor： THOMAS GROSSER ,  GERRIT KOCH ,  RALF WINKELMANN

IPC: G06F11/36

Abstract: Verifying functional correctness of a graph-based coherency verification tool (10) for logic designs of arrangements of processors and processor caches, by using trace files (12) as input for verifying memory ordering rules of a given processor architecture for accesses to the caches. Nodes in a graph (14) represent memory accesses and edges represent dependencies between them. The method comprises (i) providing a specification of a test case for a self-checking tool (50), the test case being a sequence of statements in a high-level description language format, representing memory access events and system events; and (ii) generating trace files (12) with the self-checking tool for the graph-based coherency verification tool by producing all possible permutations of trace events, which are defined by the sequence of statements in the test case. The tool uses traces files of simulations of logic descriptions as input, tracing system events, instructions, cache fetch, store commands to create a failing scenario, which allows parsing an expanded set of permutations in a returned table data structure, which can be iterated.

公开(公告)号：GB2597884A

公开(公告)日：2022-02-09

申请号：GB202116692

申请日：2020-04-02

Applicant: IBM

Inventor： MICHAEL FEE ,  RALF WINKELMANN ,  MATTHIAS KLEIN ,  CARSTEN OTTE ,  EDWARD CHENCINSKI ,  HANNO EICHELBERGER

IPC: G06F9/52 ,  G06F11/30 ,  G06F12/08 ,  G06F13/16

Abstract: The present disclosure relates to a method for a computer system comprising a plurality of processor cores, wherein a cached data item is assigned to a first core of the processor cores for exclusively executing an atomic primitive by the first core. The method comprises, while the execution of the atomic primitive is not completed by the first core, receiving from a second core at a cache controller a request for accessing the data item. In response to determining that a second request of the data item is received from a third core, of the plurality of processor cores, before receiving the request of the second core, a rejection message may be returned to the second core.