公开(公告)号：GB2532232A

公开(公告)日：2016-05-18

申请号：GB201420116

申请日：2014-11-12

Applicant: IBM

Inventor： THOMAS GROSSER ,  GERRIT KOCH ,  RALF WINKELMANN

IPC: G06F11/36

Abstract: Verifying functional correctness of a graph-based coherency verification tool (10) for logic designs of arrangements of processors and processor caches, by using trace files (12) as input for verifying memory ordering rules of a given processor architecture for accesses to the caches. Nodes in a graph (14) represent memory accesses and edges represent dependencies between them. The method comprises (i) providing a specification of a test case for a self-checking tool (50), the test case being a sequence of statements in a high-level description language format, representing memory access events and system events; and (ii) generating trace files (12) with the self-checking tool for the graph-based coherency verification tool by producing all possible permutations of trace events, which are defined by the sequence of statements in the test case. The tool uses traces files of simulations of logic descriptions as input, tracing system events, instructions, cache fetch, store commands to create a failing scenario, which allows parsing an expanded set of permutations in a returned table data structure, which can be iterated.

公开(公告)号：GB2631975A

公开(公告)日：2025-01-22

申请号：GB202311093

申请日：2023-07-20

Applicant: IBM

Inventor： YVO MULDER ,  HUIYUAN XING ,  GERRIT KOCH ,  ULRIKE LETZ

IPC: G06F11/273 ,  G06F11/22 ,  G06F11/26

Abstract: A verification environment VE monitors accesses to a cache by a device under test DUT via an interface. In response to a cache access, the verification environment modifies the cache memory to give a predefined result from the cache access. The predefined result is then returned to the device under test via the interface. The verification environment may modify the data content of the cache by generating the predetermined value. It may modify the directory state assigned to the target of the cache access. The state may be valid, dirty, speculation or coherency. It may modify the least recently used state, or a most recently used state of the target. It may modify a memory reference model of the device under test. The device under test may be a software simulation or a hardware device. The verification environment may generate a pass or a fail signal dependent on the returned result.