公开(公告)号：EP2588650A4

公开(公告)日：2014-03-19

申请号：EP11801264

申请日：2011-06-23

Applicant: MATHESON TRI GAS INC ,  IBM

Inventor： FRANCIS TERRY ARTHUR ,  HASAKA SATOSHI ,  BRABANT PAUL DAVID ,  TORRES ROBERT JR ,  HE HONG ,  REZNICEK ALEXANDER ,  ADAM THOMAS N ,  SADANA DEVENDRA K

IPC: C30B25/02 ,  C23C16/30 ,  C23C16/32 ,  C30B29/06 ,  H01L21/02

CPC classification number: H01L21/02532 ,  C23C16/30 ,  C23C16/325 ,  C30B25/02 ,  C30B29/06 ,  H01L21/0237 ,  H01L21/02529 ,  H01L21/02573 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02636

公开(公告)号：JP2005311367A

公开(公告)日：2005-11-04

申请号：JP2005119125

申请日：2005-04-18

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： KEVIN K CHAN ,  DORIS BRUCE B ,  GUARINI KATHRYN W ,  LEONG MEIKEI ,  NARASIMHA SHREESH ,  REZNICEK ALEXANDER ,  KERN LIM ,  SADANA DEVENDRA K ,  SHI LEATHEN ,  SLEIGHT JEFFREY W ,  YANG MIN

IPC: H01L27/08 ,  H01L21/02 ,  H01L21/20 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/04 ,  H01L29/76 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/7842 ,  H01L21/2022 ,  H01L21/76275 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/78687

Abstract: PROBLEM TO BE SOLVED: To provide an integrated semiconductor device formed on a substrate having different crystal orientation.
SOLUTION: A method of forming a hybrid substrate containing strained Si and a strained Si containing hybrid substrate formed by this method are provided. In the present invention, a strained Si layer is formed on a semiconductor material, a second semiconductor layer, or both of them. According to the present invention, the strained Si layer has the same crystal orientation as either of a regrown semiconductor layer or the second semiconductor layer. This method provides the hybrid substrate wherein at least one of device layers contains the strained Si.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供形成在具有不同晶体取向的基板上的集成半导体器件。 解决方案：提供一种形成含有应变Si的混合基板和通过该方法形成的包含应变的含Si混合基板的方法。 在本发明中，在半导体材料，第二半导体层或它们两者上形成应变Si层。 根据本发明，应变Si层具有与重新生长的半导体层或第二半导体层中的任一个相同的晶体取向。 该方法提供混合基板，其中装置层中的至少一个包含应变Si。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2006191029A

公开(公告)日：2006-07-20

申请号：JP2005363874

申请日：2005-12-16

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DE SOUZA JOEL P ,  OTT JOHN A ,  REZNICEK ALEXANDER ,  SADANA DEVENDRA K ,  SAENGER KATHERINE L

IPC: H01L21/02

CPC classification number: H01L21/187 ,  H01L21/76251

Abstract: PROBLEM TO BE SOLVED: To provide a method of forming a bonding interface between Si having characteristics equal to that attained by hydrophobic bonding by removing an ultra thin interface oxide remaining after hydrophobic wafer bonding between Si.
SOLUTION: The interface oxide layer in the order of about 2-3 nm is dissolved and removed by, for example, high temperature annealing at 1,300-1,330°C only for 1-5 hours. The invention is most effectively used if the Si surface of a bonding interface has a different surface orientation as, for example, the Si surface with (100) orientation is bonded to the Si surface with (110) orientation. In more generous modes of this invention, an undesired material arranged on the bonding interface of two silicon-contained semiconductor materials can be removed by a similar annealing process. The surface crystal orientation, fine structure (single crystal, polycrystal, or amorphous), and elements of two silicon-contained semiconductor materials may or may not be identical.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供通过除去Si之间的疏水性晶片接合之后残留的超薄界面氧化物，形成具有与通过疏水接合获得的特性相同的特性的Si之间的结合界面的方法。 解决方案：通过例如1300-133℃的高温退火将约2-3nm量级的界面氧化物层溶解并除去1-5小时。 如果接合界面的Si表面具有不同的表面取向，则本发明是最有效的，因为例如具有（110）取向的具有（100）取向的Si表面结合到Si表面。 在本发明的更宽泛的模式中，可以通过类似的退火工艺去除布置在两个含硅半导体材料的结合界面上的不需要的材料。 表面晶体取向，精细结构（单晶，多晶或非晶）和两个含硅半导体材料的元素可以相同也可以不相同。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2006054465A

公开(公告)日：2006-02-23

申请号：JP2005233104

申请日：2005-08-11

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： FRANK MARTIN M ,  REZNICEK ALEXANDER ,  GOUSEV EVGENI P ,  CARTIER EDUARD A

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/283

CPC classification number: H01L29/495 ,  H01L21/76254 ,  H01L21/823828 ,  H01L29/517

Abstract: PROBLEM TO BE SOLVED: To provide a technique for forming a gate stack partially at least on a semiconductor substrate which makes it possible to use various gate materials without sacrificing device performance.
SOLUTION: There is provided the method of forming a gate stack for a semiconductor electron device using the wafer bonding of at least one structure containing a high k dielectric material. The method comprises a step of selecting first and second structures each having a principal plane. At least one of or both of the first and the second structures comprise the high k dielectric material at least. Then, a bonding structure comprising at least the high k dielectric material of the gate stack is formed by joining the primary planes of the first and the second structures.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供至少部分地在半导体衬底上形成栅叠层的技术，这使得可以在不牺牲器件性能的情况下使用各种栅极材料。 解决方案：提供了使用包含高k电介质材料的至少一种结构的晶片接合形成半导体电子器件的栅极堆叠的方法。 该方法包括选择具有主平面的第一和第二结构的步骤。 第一和第二结构中的至少一个或两者至少包括高k电介质材料。 然后，通过连接第一和第二结构的主平面来形成至少包括栅叠层的高k电介质材料的键合结构。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2006041526A

公开(公告)日：2006-02-09

申请号：JP2005213971

申请日：2005-07-25

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： KEVIN K CHAN ,  DE SOUZA JOEL P ,  REZNICEK ALEXANDER ,  SADANA DEVENDRA K ,  SAENGER KATHERINE L

IPC: H01L21/76 ,  H01L21/02 ,  H01L21/265 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L21/84 ,  H01L21/76243 ,  H01L21/76267 ,  H01L27/1203 ,  H01L27/1207

Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing a device on a crystal of orientation which brings about optimal performance by providing separation by an oxygen implantation (SIMOX) method for the formation of a flat hybrid orientation semiconductor on insulator (SOI) substrate having a crystal of different orientation. SOLUTION: A method comprises steps of: selecting a substrate having a lower semiconductor layer having first crystal orientation separated from an upper semiconductor layer having second crystal orientation by a thin insulating layer; replacing the upper semiconductor layer of a selected region with epitaxial growth semiconductor having the first crystal orientation; (i) forming a padding insulating region in an epitaxial growth semiconductor material and (ii) thickening an insulating layer under the upper semiconductor layer using ion implantation and annealing methods; and forming a hybrid orientation substrate in which two semiconductor materials of different crystal orientation have substantially identical thickness and are arranged on the common padding insulating layer. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种通过提供通过氧注入（SIMOX）方法分离以形成绝缘体上的平坦混合取向半导体（SOI）的方向来制造取向晶体的装置的方法，该方法产生最佳性能 ）衬底具有不同取向的晶体。 解决方案：一种方法包括以下步骤：通过薄绝缘层，选择具有从具有第二晶体取向的上半导体层分离的具有第一晶体取向的下半导体层的衬底; 用具有第一晶体取向的外延生长半导体代替所选区域的上半导体层; （i）在外延生长半导体材料中形成填充绝缘区域，和（ii）使用离子注入和退火方法使上半导体层下方的绝缘层增厚; 以及形成混合取向基板，其中两个不同晶体取向的半导体材料具有基本上相同的厚度并且布置在公共衬垫绝缘层上。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2005136410A

公开(公告)日：2005-05-26

申请号：JP2004310704

申请日：2004-10-26

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： LEONG MEIKEI ,  REZNICEK ALEXANDER ,  YANG MIN

IPC: H01L21/822 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/04 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide a hybrid substrate, equipped with semiconductor layers, having different crystal orientations isolated by a conductive or an insulating interface.
SOLUTION: A method of providing a hybrid substrate, equipped with semiconductor layers having different crystal orientations that are isolated by a conductive or an insulating interface formed by employing semiconductor-to-semiconductor direct wafer bonding, is disclosed. The hybrid substrate may also be yielded by a method, employing a direct bonding method which provides an integrated semiconductor structure, in which various CMOSs are constructed on plane directions which enhance the performance of a device.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供配备有通过导电或绝缘界面隔离的不同晶体取向的半导体层的混合基板。 解决方案：提供一种提供混合基板的方法，该混合基板配备有通过采用半导体至半导体直接晶片接合形成的导电或绝缘界面隔离的具有不同晶体取向的半导体层。 也可以通过使用提供集成半导体结构的直接接合方法的方法来产生混合衬底，其中在平面方向上构造各种CMOS，这增强了器件的性能。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：WO2006057645A8

公开(公告)日：2006-08-03

申请号：PCT/US2004042179

申请日：2004-12-15

Applicant: IBM ,  CHAN VICTOR ,  FISCHETTI MASSIMO V ,  HERGENROTHER JOHN M ,  LEONG MEIKEI ,  RENGARAJAN RAJESH ,  REZNICEK ALEXANDER ,  SOLOMON PAUL ,  SUNG CHUN-YUNG ,  YANG MIN

Inventor： CHAN VICTOR ,  FISCHETTI MASSIMO V ,  HERGENROTHER JOHN M ,  LEONG MEIKEI ,  RENGARAJAN RAJESH ,  REZNICEK ALEXANDER ,  SOLOMON PAUL ,  SUNG CHUN-YUNG ,  YANG MIN

IPC: H01L29/02 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/04 ,  H01L29/786 ,  H01L31/109

CPC classification number: H01L29/7842 ,  H01L21/823807 ,  H01L29/045 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/78684

Abstract: The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a -containing layer having a 110 crystal orientation and a biaxial compressive strain. The term ''biaxial compressive stress'' is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing 110 layer; and creating a biaxial strain in the silicon-containing 110 layer.

Abstract translation: 本发明提供具有增强的电子和空穴迁移率的半导体材料，其包含具有110晶向和双向压缩应变的含有层。 术语“双轴压缩应力”在本文中用于描述由在制造半导体材料期间在含Si层上感应的纵向压缩应力和横向应力引起的净应力。 本发明的另一方面涉及一种形成本发明的半导体材料的方法。 本发明的方法包括提供含硅110层的步骤; 并在含硅110层中产生双轴应变。

公开(公告)号：WO2005057631A2

公开(公告)日：2005-06-23

申请号：PCT/US2004039970

申请日：2004-11-30

Applicant: IBM ,  DE SOUZA JOEL P ,  OTT JOHN A ,  REZNICEK ALEXANDER ,  SAENGER KATHERINE L

Inventor： DE SOUZA JOEL P ,  OTT JOHN A ,  REZNICEK ALEXANDER ,  SAENGER KATHERINE L

IPC: H01L21/20 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/04 ,  H01L29/10 ,  H01L29/786 ,  H01L21/00

CPC classification number: H01L29/78696 ,  H01L21/2022 ,  H01L21/76251 ,  H01L21/76275 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/045 ,  H01L29/1054 ,  H01L29/66772 ,  H01L29/78654

Abstract: A method utilizing localized amorphization and recrystallization of stacked template layers is provided for making a planar substrate having semiconductor layers of different crystallographic orientations. Also provided are hybrid­-orientation semiconductor substrate structures built with the methods of the invention, as well as such structures integrated with various CMOS circuits comprising at least two semiconductor devices disposed on different surface orientations for enhanced device performance.

Abstract translation: 提供了利用层叠模板层的局部非晶化和重结晶的方法，用于制造具有不同晶体取向的半导体层的平面基板。 还提供了利用本发明的方法构建的混合取向半导体衬底结构，以及与各种CMOS电路集成的这种结构，其包括设置在不同表面取向上的至少两个半导体器件，用于增强器件性能。

公开(公告)号：WO2007130333A2

公开(公告)日：2007-11-15

申请号：PCT/US2007010411

申请日：2007-04-30

Applicant: IBM ,  BEDELL STEPHEN W ,  DESOUZA JOEL P ,  REN ZHIBIN ,  REZNICEK ALEXANDER ,  SADANA DEVENDRA K ,  SAENGER KATHERINE L ,  SHAHIDI GHAVAM

Inventor： BEDELL STEPHEN W ,  DESOUZA JOEL P ,  REN ZHIBIN ,  REZNICEK ALEXANDER ,  SADANA DEVENDRA K ,  SAENGER KATHERINE L ,  SHAHIDI GHAVAM

IPC: H01L21/8234

CPC classification number: H01L29/66628 ,  H01L21/26513 ,  H01L21/324 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7848 ,  H01L29/78618 ,  H01L29/78684 ,  Y10S438/909 ,  Y10S438/943

Abstract: This invention teaches methods of combining ion implantation steps with in situ or ex situ heat treatments to avoid and/or minimize implant-induced amorphization (a potential problem for source/drain (SfD) regions in FETs in ultrathin silicon on insulator layers) and implant-induced plastic relaxation of strained S/D regions (a potential problem for strained channel FETs in which the channel strain is provided by embedded S/D regions lattice mismatched with an underlying substrate layer). In a first embodiment, ion implantation is combined with in situ heat treatment by performing the ion implantation at elevated temperature. In a second embodiment, ion implantation is combined withex situ heat treatments in a "divided-dose-anneal-in-between" (DDAB) scheme that avoids the need for tooling capable of performing hot implants.

Abstract translation: 本发明教导了将离子注入步骤与原位或非原位热处理组合以避免和/或最小化植入物诱导的非晶化（在绝缘体上的超薄硅层中的FET中的源/漏（SfD）区域的潜在问题）和植入物 诱导的应变S / D区域的塑性弛豫（对于通道应变由嵌入的S / D区域与下面的基底层不匹配而提供的应变通道FET的潜在问题）。 在第一实施例中，通过在升高的温度下进行离子注入将离子注入与原位热处理组合。 在第二实施例中，离子注入在“分剂量退火中间”（DDAB）方案中组合了原位热处理，避免了对能够进行热植入的加工的需要。

公开(公告)号：WO2015032274A9

公开(公告)日：2016-03-24

申请号：PCT/CN2014084756

申请日：2014-08-20

Applicant: IBM ,  IBM CHINA CO LTD

Inventor： NACZAS SEBASTIAN ,  PARUCHURI VAMSI ,  REZNICEK ALEXANDER ,  SCHEPIS DOMINIC J

IPC: H01L29/78

CPC classification number: H01L23/535 ,  H01L29/0673 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/66795 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A low resistance contact to a finFET source/drain can be achieved by forming a defect free surface on which to form such contact. The fins of a finFET can be exposed to epitaxial growth conditions to increase the bulk of semiconductive material in the source/drain. Facing growth fronts can merge or can form unmerged facets. A dielectric material can fill voids within the source drain region. A trench spaced from the finFET gate can expose the top portion of faceted epitaxial growth on fins within said trench, such top portions separated by a smooth dielectric surface. A silicon layer selectively formed on the top portions exposed within the trench can be converted to a semiconductor-metal layer, connecting such contact with individual fins in the source drain region.

Abstract translation: 可以通过形成在其上形成这种接触的无缺陷表面来实现对finFET源极/漏极的低电阻接触。 finFET的翅片可以暴露于外延生长条件以增加源极/漏极中的半导体材料的体积。 面对增长的前沿可以合并或形成未成熟的方面。 电介质材料可以填充源极漏极区域内的空隙。 与finFET栅极隔开的沟槽可以暴露在所述沟槽内的鳍片上的刻面外延生长的顶部，这些顶部由光滑电介质表面分开。 选择性地形成在暴露在沟槽内的顶部上的硅层可以转化为半导体金属层，将这种接触与源极漏极区域中的各个鳍连接。