Inter-si pseudo hydrophobic wafer bonding using solution of interface bonding oxide and hydrophilic si surface
    3.
    发明专利
    Inter-si pseudo hydrophobic wafer bonding using solution of interface bonding oxide and hydrophilic si surface 有权
    界面结合氧化物和疏水性SI表面的解决方案的INTER-SI PSEUDO HYDROPHOBIC WAFER BONDING

    公开(公告)号:JP2006191029A

    公开(公告)日:2006-07-20

    申请号:JP2005363874

    申请日:2005-12-16

    CPC classification number: H01L21/187 H01L21/76251

    Abstract: PROBLEM TO BE SOLVED: To provide a method of forming a bonding interface between Si having characteristics equal to that attained by hydrophobic bonding by removing an ultra thin interface oxide remaining after hydrophobic wafer bonding between Si.
    SOLUTION: The interface oxide layer in the order of about 2-3 nm is dissolved and removed by, for example, high temperature annealing at 1,300-1,330°C only for 1-5 hours. The invention is most effectively used if the Si surface of a bonding interface has a different surface orientation as, for example, the Si surface with (100) orientation is bonded to the Si surface with (110) orientation. In more generous modes of this invention, an undesired material arranged on the bonding interface of two silicon-contained semiconductor materials can be removed by a similar annealing process. The surface crystal orientation, fine structure (single crystal, polycrystal, or amorphous), and elements of two silicon-contained semiconductor materials may or may not be identical.
    COPYRIGHT: (C)2006,JPO&NCIPI

    Abstract translation: 要解决的问题:提供通过除去Si之间的疏水性晶片接合之后残留的超薄界面氧化物,形成具有与通过疏水接合获得的特性相同的特性的Si之间的结合界面的方法。 解决方案:通过例如1300-133℃的高温退火将约2-3nm量级的界面氧化物层溶解并除去1-5小时。 如果接合界面的Si表面具有不同的表面取向,则本发明是最有效的,因为例如具有(110)取向的具有(100)取向的Si表面结合到Si表面。 在本发明的更宽泛的模式中,可以通过类似的退火工艺去除布置在两个含硅半导体材料的结合界面上的不需要的材料。 表面晶体取向,精细结构(单晶,多晶或非晶)和两个含硅半导体材料的元素可以相同也可以不相同。 版权所有(C)2006,JPO&NCIPI

    Semiconductor/dielectric/semiconductor device structure manufactured by wafer bonding
    4.
    发明专利
    Semiconductor/dielectric/semiconductor device structure manufactured by wafer bonding 有权
    半导体/电介质/半导体器件结构由波形焊接制造

    公开(公告)号:JP2006054465A

    公开(公告)日:2006-02-23

    申请号:JP2005233104

    申请日:2005-08-11

    CPC classification number: H01L29/495 H01L21/76254 H01L21/823828 H01L29/517

    Abstract: PROBLEM TO BE SOLVED: To provide a technique for forming a gate stack partially at least on a semiconductor substrate which makes it possible to use various gate materials without sacrificing device performance.
    SOLUTION: There is provided the method of forming a gate stack for a semiconductor electron device using the wafer bonding of at least one structure containing a high k dielectric material. The method comprises a step of selecting first and second structures each having a principal plane. At least one of or both of the first and the second structures comprise the high k dielectric material at least. Then, a bonding structure comprising at least the high k dielectric material of the gate stack is formed by joining the primary planes of the first and the second structures.
    COPYRIGHT: (C)2006,JPO&NCIPI

    Abstract translation: 要解决的问题:提供至少部分地在半导体衬底上形成栅叠层的技术,这使得可以在不牺牲器件性能的情况下使用各种栅极材料。 解决方案:提供了使用包含高k电介质材料的至少一种结构的晶片接合形成半导体电子器件的栅极堆叠的方法。 该方法包括选择具有主平面的第一和第二结构的步骤。 第一和第二结构中的至少一个或两者至少包括高k电介质材料。 然后,通过连接第一和第二结构的主平面来形成至少包括栅叠层的高k电介质材料的键合结构。 版权所有(C)2006,JPO&NCIPI

    Method of forming integrated semiconductor structure (double simox hybrid orientation technic (hot) substrate)
    5.
    发明专利
    Method of forming integrated semiconductor structure (double simox hybrid orientation technic (hot) substrate) 有权
    形成集成半导体结构的方法(双SIMOX混合定向技术(热)衬底)

    公开(公告)号:JP2006041526A

    公开(公告)日:2006-02-09

    申请号:JP2005213971

    申请日:2005-07-25

    Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing a device on a crystal of orientation which brings about optimal performance by providing separation by an oxygen implantation (SIMOX) method for the formation of a flat hybrid orientation semiconductor on insulator (SOI) substrate having a crystal of different orientation. SOLUTION: A method comprises steps of: selecting a substrate having a lower semiconductor layer having first crystal orientation separated from an upper semiconductor layer having second crystal orientation by a thin insulating layer; replacing the upper semiconductor layer of a selected region with epitaxial growth semiconductor having the first crystal orientation; (i) forming a padding insulating region in an epitaxial growth semiconductor material and (ii) thickening an insulating layer under the upper semiconductor layer using ion implantation and annealing methods; and forming a hybrid orientation substrate in which two semiconductor materials of different crystal orientation have substantially identical thickness and are arranged on the common padding insulating layer. COPYRIGHT: (C)2006,JPO&NCIPI

    Abstract translation: 要解决的问题:提供一种通过提供通过氧注入(SIMOX)方法分离以形成绝缘体上的平坦混合取向半导体(SOI)的方向来制造取向晶体的装置的方法,该方法产生最佳性能 )衬底具有不同取向的晶体。 解决方案:一种方法包括以下步骤:通过薄绝缘层,选择具有从具有第二晶体取向的上半导体层分离的具有第一晶体取向的下半导体层的衬底; 用具有第一晶体取向的外延生长半导体代替所选区域的上半导体层; (i)在外延生长半导体材料中形成填充绝缘区域,和(ii)使用离子注入和退火方法使上半导体层下方的绝缘层增厚; 以及形成混合取向基板,其中两个不同晶体取向的半导体材料具有基本上相同的厚度并且布置在公共衬垫绝缘层上。 版权所有(C)2006,JPO&NCIPI

    LOCALLY RAISED EPITAXY FOR IMPROVED CONTACT BY LOCAL SILICON CAPPING DURING TRENCH SILICIDE PROCESSINGS
    10.
    发明申请
    LOCALLY RAISED EPITAXY FOR IMPROVED CONTACT BY LOCAL SILICON CAPPING DURING TRENCH SILICIDE PROCESSINGS 审中-公开
    本地硅胶加工过程中本地硅填料的局部放大外观

    公开(公告)号:WO2015032274A9

    公开(公告)日:2016-03-24

    申请号:PCT/CN2014084756

    申请日:2014-08-20

    Abstract: A low resistance contact to a finFET source/drain can be achieved by forming a defect free surface on which to form such contact. The fins of a finFET can be exposed to epitaxial growth conditions to increase the bulk of semiconductive material in the source/drain. Facing growth fronts can merge or can form unmerged facets. A dielectric material can fill voids within the source drain region. A trench spaced from the finFET gate can expose the top portion of faceted epitaxial growth on fins within said trench, such top portions separated by a smooth dielectric surface. A silicon layer selectively formed on the top portions exposed within the trench can be converted to a semiconductor-metal layer, connecting such contact with individual fins in the source drain region.

    Abstract translation: 可以通过形成在其上形成这种接触的无缺陷表面来实现对finFET源极/漏极的低电阻接触。 finFET的翅片可以暴露于外延生长条件以增加源极/漏极中的半导体材料的体积。 面对增长的前沿可以合并或形成未成熟的方面。 电介质材料可以填充源极漏极区域内的空隙。 与finFET栅极隔开的沟槽可以暴露在所述沟槽内的鳍片上的刻面外延生长的顶部,这些顶部由光滑电介质表面分开。 选择性地形成在暴露在沟槽内的顶部上的硅层可以转化为半导体金属层,将这种接触与源极漏极区域中的各个鳍连接。

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