公开(公告)号：GB2547397A

公开(公告)日：2017-08-16

申请号：GB201709198

申请日：2015-11-13

Applicant: IBM

Inventor： ROBERT SONNELITTER III ,  EKATERINA AMBROLADZE ,  ARTHUR O'NEILL JR ,  MICHAEL FEE ,  DEANNA POSTLES DUNN BERGER

IPC: G06F12/0815 ,  G06F12/084

Abstract: Topology of clusters of processors of a computer configuration, configured to support any of a plurality of cache coherency protocols, is discovered at initialization time to determine which one of the plurality of cache coherency protocols is to be used to handle coherency requests of the configuration

公开(公告)号：GB2547397B

公开(公告)日：2017-11-29

申请号：GB201709198

申请日：2015-11-13

Applicant: IBM

Inventor： ROBERT SONNELITTER III ,  EKATERINA AMBROLADZE ,  ARTHUR O'NEILL JR ,  MICHAEL FEE ,  DEANNA POSTLES DUNN BERGER

IPC: G06F12/0815 ,  G06F12/084

Abstract: Topology of clusters of processors of a computer configuration, configured to support any of a plurality of cache coherency protocols, is discovered at initialization time to determine which one of the plurality of cache coherency protocols is to be used to handle coherency requests of the configuration.