公开(公告)号：GB2633234A

公开(公告)日：2025-03-05

申请号：GB202416054

申请日：2023-03-30

Applicant: IBM

Inventor： ASHRAF ELSHARIF ,  RICHARD BRANCIFORTE ,  GREGORY ALEXANDER ,  DEANNA POSTLES DUNN BERGER ,  TIMOTHY BRONSON ,  AARON TSAI ,  TAYLOR PRITCHARD ,  MARKUS KALTENBACH ,  CHRISTIAN JACOBI ,  MICHAEL BLAKE

IPC: G06F12/0811 ,  G06F12/0897

Abstract: A computer system includes a processor core and a memory system in signal communication with the processor core. The memory system includes a first cache and a second cache. The first cache is arranged at a first level of a hierarchy in the memory system and is configured to store a plurality of first-cache entries. The second cache is arranged at a second level of the hierarchy that is lower than the first level, and stores a plurality of second-cache entries. The first cache maintains a directory that contains information for each of the first-cache entries. The second cache maintains a shadow pointer directory (SPD) that includes one or more SPD entries that maps each of the first-cache entries to a corresponding second cache entry at a lower-level cache location.

公开(公告)号：GB2547397A

公开(公告)日：2017-08-16

申请号：GB201709198

申请日：2015-11-13

Applicant: IBM

Inventor： ROBERT SONNELITTER III ,  EKATERINA AMBROLADZE ,  ARTHUR O'NEILL JR ,  MICHAEL FEE ,  DEANNA POSTLES DUNN BERGER

IPC: G06F12/0815 ,  G06F12/084

Abstract: Topology of clusters of processors of a computer configuration, configured to support any of a plurality of cache coherency protocols, is discovered at initialization time to determine which one of the plurality of cache coherency protocols is to be used to handle coherency requests of the configuration

公开(公告)号：GB2547397B

公开(公告)日：2017-11-29

申请号：GB201709198

申请日：2015-11-13

Applicant: IBM

Inventor： ROBERT SONNELITTER III ,  EKATERINA AMBROLADZE ,  ARTHUR O'NEILL JR ,  MICHAEL FEE ,  DEANNA POSTLES DUNN BERGER

IPC: G06F12/0815 ,  G06F12/084

Abstract: Topology of clusters of processors of a computer configuration, configured to support any of a plurality of cache coherency protocols, is discovered at initialization time to determine which one of the plurality of cache coherency protocols is to be used to handle coherency requests of the configuration.