公开(公告)号：DE3484285D1

公开(公告)日：1991-04-25

申请号：DE3484285

申请日：1984-03-30

Applicant: IBM

Inventor： OMAN PRICE WARD ,  RINALDI MARK ANTHONY ,  RUSSO VITO WILLIAM ,  SALYER GREGORY

IPC: G06F9/38 ,  G06F9/22 ,  G06F9/28 ,  G06F13/42

Abstract: A uniprocessor is formed on plural independently controlled chips (26, 28,30) each including a primary instruction driven controller (84) and a secondary error driven self-sequencing controller (102). Each instruction is supplied in parallel to each primary controller which generates an EXIT signal, as it completes execution, to a common external EXIT line (62). Hardware (116) monitors the local EXIT signal and the common EXIT line state and activates the secondary controller, when a mismatch is detected, to set an on-chip reset predominant error latch (124) driving a common external ERROR line (64), an ERROR-state on which also sets the latches and activates any inactive secondary controller to drive its chip to a first predetermined state and to reset its latch. When no ERROR signal remains, the secondary controllers cycle in synchronism through an ERROR routine, exiting to instruction control.