公开(公告)号：DE2524046A1

公开(公告)日：1976-01-15

申请号：DE2524046

申请日：1975-05-30

Applicant: IBM

Inventor： HOLMES JUN ARTHUR WILBERT ,  OMAN PRICE WARD ,  PADDOCK RICHARD CHARLES ,  PRICE DONALD WALTER

IPC: G06F9/46 ,  G06F9/38 ,  G06F15/16 ,  G06F15/177 ,  G06F15/80 ,  G06F9/10 ,  G06F13/06

Abstract: A processor including a plurality of synchronized subprocessors, each implemented on an integrated circuit substrate and each having an instruction register and instruction executing circuits for independently executing a portion of the functions required by an instruction being simultaneously executed by each subprocessor. Execution is initiated and synchronized by simultaneously loading the same instruction into each subprocessor.

公开(公告)号：MY121358A

公开(公告)日：2006-01-28

申请号：MYPI9800946

申请日：1998-03-04

Applicant: IBM

Inventor： BASS BRIAN MITCHELL ,  HUBBARD JAMES ALLISON ,  OMAN PRICE WARD ,  PITA FRANK J

IPC: G06F3/00 ,  G06F13/00 ,  G06F13/40

Abstract: METHOD AND SYSTEM FOR CONTROLLING THE STATE OF A SYSTEM BUS DURING LIVE INSERTION AND REMOVAL OF A PLUGGABLE FEATURE CARD (FC) BY DRIVING CONTROL SIGNALS, WHICH ARE TRANSFERRED OVER THE SYSTEM BUS, TO AN ACTIVE SIGNAL LEVEL, OR BY DRIVING DOWN LEVEL ACTIVE CONTROL SIGNALS TO A LOW SIGNAL LEVEL NEAR GROUND LEVEL. BY THIS MECHANISM, THE SYSTEM BUS BECOMES IMMUNE TO SIGNAL DISTURBANCES AND THEREBY ALLOWS PLUGGABLE UNITS TO BE LIVE INSERTED AND REMOVED WITHOUT CAUSING ADVERSE EFFECTS TO THE SYSTEM SUCH AS A SYSTEM RESET OR COMPROMISE OF DATA INTEGRITY. DURING LIVE INSERTION OR REMOVAL, A LIVE INSERTION BUS CONTROLLER (LIBC) ACQUIRES ACCESS TO THE SYSTEM BUS THROUGH ITS INTERFACE WITH A SYSTEM BUS CONTROLLER (SBC), AFTER IT HAS BEEN SIGNALLED BY A LIVE INSERTION MECHANISM ASSOCIATED WITH THE FC THAT THE FC IS IN THE PROCESS OF BEING LIVE INSERTED OR REMOVED. AFTER SYSTEM BUS ACCESS HAS BEEN ACQUIRED BY THE LIBC AND THE LIBC HAS TAKEN OVER THE CONTROL OF THE SYSTEM BUS, IT DRIVES A SUBSET OF THE SYSTEM BUS SET OF CONTROL SIGNALS TO A STATE THAT IS IMMUNE FROM INSERTION/REMOVAL SIGNAL DISTURBANCE. IN PARALLEL, THE LIBC EFFECTS SUSPENSION OF RUNNING TIMEOUT AND WATCHDOG OPERATIONS CURRENTLY BEING PERFORMED BY THE SBC. WHEN THE LIBC IS INFORMED THAT THE INSERTION PROCESS HAS BEEN COMPLETED, THE SBC AGAIN ACQUIRES CONTROL OF THE SYSTEM BUS. THE SAME PROCEDURAL STEPS ARE PERFORMED IN CASE OF REMOVAL OF AN FC.(FIG. 2)

公开(公告)号：DE3484285D1

公开(公告)日：1991-04-25

申请号：DE3484285

申请日：1984-03-30

Applicant: IBM

Inventor： OMAN PRICE WARD ,  RINALDI MARK ANTHONY ,  RUSSO VITO WILLIAM ,  SALYER GREGORY

IPC: G06F9/38 ,  G06F9/22 ,  G06F9/28 ,  G06F13/42

Abstract: A uniprocessor is formed on plural independently controlled chips (26, 28,30) each including a primary instruction driven controller (84) and a secondary error driven self-sequencing controller (102). Each instruction is supplied in parallel to each primary controller which generates an EXIT signal, as it completes execution, to a common external EXIT line (62). Hardware (116) monitors the local EXIT signal and the common EXIT line state and activates the secondary controller, when a mismatch is detected, to set an on-chip reset predominant error latch (124) driving a common external ERROR line (64), an ERROR-state on which also sets the latches and activates any inactive secondary controller to drive its chip to a first predetermined state and to reset its latch. When no ERROR signal remains, the secondary controllers cycle in synchronism through an ERROR routine, exiting to instruction control.