公开(公告)号：MY106699A

公开(公告)日：1995-07-31

申请号：MYPI19900468

申请日：1990-03-24

Applicant: IBM

Inventor： NICKY CHAU-CHUN LU ,  SANG HOO DHONG ,  WEI HWANG

IPC: G11C11/408 ,  G11C11/407 ,  H03K5/02 ,  H03K17/00

Abstract: TWO EMBODIMENTS OF A WORDLINE BOOST CLOCK CIRCUIT THAT CAN BE USED IN HIGH SPEED DRAM CIRCUITS ARE DISCLOSED. THE CLOCK CIRCUITS REQUIRE ONLY ONE BOOST CAPACITOR AND DISCHARGE THE WORDLINES FASTER, IMPROVING THE DRAM ACCESS TIME. THE BASIC FEATURE OF THE CLOCK CIRCUIT IS IN THE FLOATING GATE STRUCTURE OF THE NMOS DEVICE WHICH DRIVES THE LOAD TO NEGATIVE DURING THE BOOSTING. IN THE FIRST EMBODIMENT OF THE CLOCK, THE GATE OF A FIRST DEVICE IS CONNECTED TO A FIRST NODE THROUGH A SECOND DEVICE. A SECOND NODE, CONNECTED TO A WORDLINE, IS DISCHARGED THROUGH THE FIRST AND A THIRD DEVICE WHEN A THIRD NODE IS HIGH WITH A FOURTH NODE LOW. AFTER A SUFFICIENT DISCHARGE OF THE SECOND NODE, THE FOURTH NODE IS PULLED TO VDD TURNING THE SECOND DEVICE ON AND A FOURTH DEVICE OFF. THE FIRST (NMOS) TRANSISTOR HAS ITS GATE DRAIN CONNECTED TOGETHER AND FORM A DIODE. WHEN A BOOST CAPACITOR PULLS THE THIRD NODE DOWN TO NEGATIVE, THE FIRST DEVICE STAYS COMPLETELY OFF BECAUSE OF ITS DIODE CONFIGURATION AND THE SECOND NODE IS PULLED TO NEGATIVE THROUGH THE THIRD DEVICE. IN THE SECOND EMBODIMENT, A FIRST DEVICE IS CONNECTED BETWEEN A BOOST CAPACITOR AND A SECOND NODE. THE LOAD IS DISCHARGED THROUGH A THIRD DEVICE WITH A FOURTH DEVICE ON BUT A FIRST AND SECOND DEVICE OFF. AFTER A SUFFICIENT DISCHARGE OF THE LOAD, A FOURTH DEVICE IS TURNED OFF BUT A SECOND DEVICE IS TURNED ON; MAKING THE THIRD DEVICE A DIODE. WHEN A FIFTH NODE IS PULLED TO GROUND, THE SECOND NODE IS PULLED DOWN TO NEGATIVE WITH THE FIRST DEVICE ON. IN THE SECOND EMBODIMENT CIRCUIT, THE LOAD DISCHARGES THROUGH ONLY ONE NMOS DEVICE AND CONSEQUENTLY DISHARGES FASTER THAN THE CIRCUIT OF THE FIRST EMBODIMENT.(FIG. 2)

公开(公告)号：MY104092A

公开(公告)日：1993-11-30

申请号：MYPI19890937

申请日：1989-07-10

Applicant: IBM

Inventor： NICKY CHAU-CHUN LU ,  SANG HOO DHONG ,  WALTER HARVEY HENKELS

IPC: G11C11/405 ,  G11C11/24 ,  H01L21/265 ,  G11C11/404 ,  G11C11/409 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/108

Abstract: A COMPLEMENTARY MOS ONE-CAPACITOR DYNAMIC RAM CELL WHICH OPERATES WITH A NON-BOOSTED WORDLINE WITHOUT A THRESHOLD LOSS PROBLEM AND WHICH INCLUDES ONE STORAGE CAPACITOR (30) AND N- AND P-TYPE TRANSFER DEVICES (10, 12 AND 14, 16), CONNECTED TO THE STORAGE CAPACITOR WHICH FUNCTION AS TWO COMPLEMENTARY TRANSISTOR DEVICES HAVING GATES (18, 22 AND 20, 24) CONTROLLED BY COMPLEMENTARY SIGNALS ON THE RAM WORDLINES.(FIG. 1)