公开(公告)号：MY104092A

公开(公告)日：1993-11-30

申请号：MYPI19890937

申请日：1989-07-10

Applicant: IBM

Inventor： NICKY CHAU-CHUN LU ,  SANG HOO DHONG ,  WALTER HARVEY HENKELS

IPC: G11C11/405 ,  G11C11/24 ,  H01L21/265 ,  G11C11/404 ,  G11C11/409 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/108

Abstract: A COMPLEMENTARY MOS ONE-CAPACITOR DYNAMIC RAM CELL WHICH OPERATES WITH A NON-BOOSTED WORDLINE WITHOUT A THRESHOLD LOSS PROBLEM AND WHICH INCLUDES ONE STORAGE CAPACITOR (30) AND N- AND P-TYPE TRANSFER DEVICES (10, 12 AND 14, 16), CONNECTED TO THE STORAGE CAPACITOR WHICH FUNCTION AS TWO COMPLEMENTARY TRANSISTOR DEVICES HAVING GATES (18, 22 AND 20, 24) CONTROLLED BY COMPLEMENTARY SIGNALS ON THE RAM WORDLINES.(FIG. 1)