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    Verifying logic design of a processor with an instruction pipeline by comparing the output from first and second instances of the design
    2.
    发明专利
    Verifying logic design of a processor with an instruction pipeline by comparing the output from first and second instances of the design 未知

    公开(公告)号：GB2508233A

    公开(公告)日：2014-05-28

    申请号：GB201221290

    申请日：2012-11-27

    Applicant: IBM

    Inventor： KRAUTZ UDO ,  SCHMIDT ULRIKE ,  BOERSMA MAARTEN

    IPC: G06F17/50

    Abstract: A logic design for a processor execution unit includes an instruction pipeline 10 with one or more pipeline stages 12 for executing a plurality of instructions. A method of formal verification of the logic design involves selecting an instruction from the plurality of instructions and may verify the processing of that instruction using formal model checking. A design under test is created by using a first 30 and a second 32 instance of the logic design. The first instance 30 is initialized with defined values in each instruction pipeline stage and the second instance 32 with random initial values in each pipeline stage. The instruction is then simultaneously issued to each instance, executed and a comparison of the results output from the instruction pipelines is made 16. If the instruction was verified by formal model checking, approving the correctness of the logic design if the comparison result is true. If the instruction was not verifiable by formal model checking, approving the correctness of a sequenced computation if the comparison result is true.

    Verifying logic design of a processor with an instruction pipeline by comparing the output from first and second instances of the design
    3.
    发明专利
    Verifying logic design of a processor with an instruction pipeline by comparing the output from first and second instances of the design 未知

    公开(公告)号：GB2508970A

    公开(公告)日：2014-06-18

    申请号：GB201318702

    申请日：2013-10-23

    Applicant: IBM

    Inventor： KRAUTZ UDO ,  SCHMIDT ULRIKE ,  BOERSMA MAARTEN

    IPC: G06F17/50

    Abstract: A logic design for a processor execution unit includes an instruction pipeline 10 with one or more pipeline stages 12 for executing a plurality of instructions. A method of formal verification of the logic design involves selecting an instruction from the plurality of instructions and may verify the processing of that instruction using formal model checking. A design under test is created by using a first 30 and a second 32 instance of the logic design. The first instance 30 is initialized with defined values in each instruction pipeline stage and the second instance 32 with random initial values in each pipeline stage. The instruction is then simultaneously issued to each instance, executed and a comparison of the results output from the instruction pipelines is made 16. If the instruction was verified by formal model checking, approving the correctness of the logic design if the comparison result is true. If the instruction was not verifiable by formal model checking, approving the correctness of a sequenced computation if the comparison result is true.

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