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    COMPUTERSYSTEM UND PROZESSOR ZUR HANDHABUNG VON ANWEISUNGEN ZUR AKKUMULATION VON REGISTERERGEBNISSEN IN EINEM MIKROPROZESSOR
    2.
    发明专利
    COMPUTERSYSTEM UND PROZESSOR ZUR HANDHABUNG VON ANWEISUNGEN ZUR AKKUMULATION VON REGISTERERGEBNISSEN IN EINEM MIKROPROZESSOR 未知

    公开(公告)号：DE112020004071B4

    公开(公告)日：2025-04-24

    申请号：DE112020004071

    申请日：2020-07-21

    Applicant: IBM

    Inventor： THOMPTO BRIAN ,  BOERSMA MAARTEN ,  WAGNER ANDREAS ,  MOREIRA JOSE ,  LE HUNG ,  MUELLER SILVIA ,  NGUYEN DUNG

    IPC: G06F9/30 ,  G06F9/38

    Abstract: Ein Computersystem, ein Prozessor und ein Verfahren zur Verarbeitung von Informationen sind offenbart, die zumindest einen Computerprozessor; eine dem mindestens einen Prozessor zugeordnete Hauptregisterdatei, wobei die Hauptregisterdatei mehrere Einträge zum Speichern von Daten, einen oder mehrere Schreibanschlüsse zum Schreiben von Daten in die Hauptregisterdateieinträge und einen oder mehrere Leseanschlüsse zum Lesen von Daten aus den Hauptregisterdateieinträgen aufweist; eine oder mehrere Ausführeinheiten, die eine komplexe Mathematikausführeinheit einschließen; und mindestens eine Akkumulatorregisterdatei aufweisen, die mehrere Einträge zum Speichern von Daten aufweist. Die Ergebnisse der komplexen Mathematikausführeinheit werden gemäß einem Aspekt in die Akkumulatorregisterdatei, vorzugsweise mehrmals in den gleichen Akkumulatorregisterdateieintrag geschrieben, und die Daten aus der Akkumulatorregisterdatei werden in die Hauptregisterdatei geschrieben.

    Verifying logic design of a processor with an instruction pipeline by comparing the output from first and second instances of the design
    3.
    发明专利
    Verifying logic design of a processor with an instruction pipeline by comparing the output from first and second instances of the design 未知

    公开(公告)号：GB2508233A

    公开(公告)日：2014-05-28

    申请号：GB201221290

    申请日：2012-11-27

    Applicant: IBM

    Inventor： KRAUTZ UDO ,  SCHMIDT ULRIKE ,  BOERSMA MAARTEN

    IPC: G06F17/50

    Abstract: A logic design for a processor execution unit includes an instruction pipeline 10 with one or more pipeline stages 12 for executing a plurality of instructions. A method of formal verification of the logic design involves selecting an instruction from the plurality of instructions and may verify the processing of that instruction using formal model checking. A design under test is created by using a first 30 and a second 32 instance of the logic design. The first instance 30 is initialized with defined values in each instruction pipeline stage and the second instance 32 with random initial values in each pipeline stage. The instruction is then simultaneously issued to each instance, executed and a comparison of the results output from the instruction pipelines is made 16. If the instruction was verified by formal model checking, approving the correctness of the logic design if the comparison result is true. If the instruction was not verifiable by formal model checking, approving the correctness of a sequenced computation if the comparison result is true.

    Method and system for pipeline depth exploration in a register transfer level design description of an electronic circuit
    5.
    发明专利
    Method and system for pipeline depth exploration in a register transfer level design description of an electronic circuit 未知

    公开(公告)号：GB2523188A

    公开(公告)日：2015-08-19

    申请号：GB201402849

    申请日：2014-02-18

    Applicant: IBM

    Inventor： SCHROEDER FRIEDRICH ,  BOERSMA MAARTEN ,  FUCHS THOMAS ,  LANG DAVID

    IPC: G06F17/50

    Abstract: An improved method and system are provided for pipeline depth exploration in a register transfer level design description of an electronic circuit. The method comprises providing a list of input registers and output registers for the circuit design to be modified S100, traversing output connections paths for each input register and replacing any register in the output connection paths by a respective wire unless the register is contained in the list of output registers S110. An initial total cycle time value for the modified registerless circuit design is determined, accounting for a register latch insertion delay time value S120. A gate level description for the modified circuit design is obtained by macro synthesis with the initial total cycle time value S130, and the total cycle time value for the modified circuit design is varied to determine theoretical limit of the modified circuit design S140. The theoretical limit of the modified circuit design is realized when negative slacks are present in the macro synthesis of the gate level description for the modified circuit design with the corresponding total cycle time value S150. The pipeline depth of the circuit design may be reduced, if said total cycle time value of the modified circuit design is lower than a threshold.

    Verifying logic design of a processor with an instruction pipeline by comparing the output from first and second instances of the design
    6.
    发明专利
    Verifying logic design of a processor with an instruction pipeline by comparing the output from first and second instances of the design 未知

    公开(公告)号：GB2508970A

    公开(公告)日：2014-06-18

    申请号：GB201318702

    申请日：2013-10-23

    Applicant: IBM

    Inventor： KRAUTZ UDO ,  SCHMIDT ULRIKE ,  BOERSMA MAARTEN

    IPC: G06F17/50

    Abstract: A logic design for a processor execution unit includes an instruction pipeline 10 with one or more pipeline stages 12 for executing a plurality of instructions. A method of formal verification of the logic design involves selecting an instruction from the plurality of instructions and may verify the processing of that instruction using formal model checking. A design under test is created by using a first 30 and a second 32 instance of the logic design. The first instance 30 is initialized with defined values in each instruction pipeline stage and the second instance 32 with random initial values in each pipeline stage. The instruction is then simultaneously issued to each instance, executed and a comparison of the results output from the instruction pipelines is made 16. If the instruction was verified by formal model checking, approving the correctness of the logic design if the comparison result is true. If the instruction was not verifiable by formal model checking, approving the correctness of a sequenced computation if the comparison result is true.

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