公开(公告)号：WO02069164A2

公开(公告)日：2002-09-06

申请号：PCT/GB0200752

申请日：2002-02-20

Applicant: IBM ,  IBM UK

Inventor： SCHUSTER STANLEY ,  COOK PETER

IPC: G06F13/42 ,  G06F9/38

CPC classification number: G06F9/3869 ,  G06F9/3871

Abstract: An interface between synchronous and asynchronous data transfer includes a plurality of stages coupled to each other to form a pipeline for data transfer. The plurality of stages include a first stage which performs synchronous to asynchronous data transfer, at least one intermediate stage which performs asynchronous to asynchronous data transfer and a last stage which performs asynchronous to synchronous data transfer. A synchronous clock path propagates a timing signal across the plurality of stages to enable the first and last stages to perform operations when the timing signal is present at that stage.

Abstract translation: 同步和异步数据传输之间的接口包括彼此耦合的多个级以形成用于数据传输的流水线。 多个级包括执行与异步数据传输同步的第一级，执行异步到异步数据传输的至少一个中间级和执行异步到同步数据传输的最后级。 同步时钟路径跨越多个级传播定时信号，以使得第一级和最后级在定时信号出现在该级时执行操作。

公开(公告)号：CA2436410A1

公开(公告)日：2002-09-06

申请号：CA2436410

申请日：2002-02-20

Applicant: IBM

Inventor： SCHUSTER STANLEY ,  COOK PETER

IPC: G06F13/42 ,  G06F9/38

Abstract: An interface between synchronous and asynchronous data transfer includes a plurality of stages coupled to each other to form a pipeline for data transfer. The plurality of stages include a first stage which performs synchronous to asynchronous data transfer, at least one intermediate stage which performs asynchronous to asynchronous data transfer and a last stage which performs asynchronous to synchronous data transfer. A synchronous cloc k path propagates a timing signal across the plurality of stages to enable the first and last stages to perform operations when the timing signal is presen t at that stage.

公开(公告)号：DE60202749D1

公开(公告)日：2005-03-03

申请号：DE60202749

申请日：2002-02-20

Applicant: IBM

Inventor： SCHUSTER STANLEY ,  COOK PETER

IPC: G06F13/42 ,  G06F9/38

Abstract: An interface between synchronous and asynchronous data transfer includes a plurality of stages coupled to each other to form a pipeline for data transfer. The plurality of stages include a first stage which performs synchronous to asynchronous data transfer, at least one intermediate stage which performs asynchronous to asynchronous data transfer and a last stage which performs asynchronous to synchronous data transfer. A synchronous clock path propagates a timing signal across the plurality of stages to enable the first and last stages to perform operations when the timing signal is present at that stage.

公开(公告)号：AT288104T

公开(公告)日：2005-02-15

申请号：AT02700456

申请日：2002-02-20

Applicant: IBM

Inventor： SCHUSTER STANLEY ,  COOK PETER

IPC: G06F13/42 ,  G06F9/38

Abstract: An interface between synchronous and asynchronous data transfer includes a plurality of stages coupled to each other to form a pipeline for data transfer. The plurality of stages include a first stage which performs synchronous to asynchronous data transfer, at least one intermediate stage which performs asynchronous to asynchronous data transfer and a last stage which performs asynchronous to synchronous data transfer. A synchronous clock path propagates a timing signal across the plurality of stages to enable the first and last stages to perform operations when the timing signal is present at that stage.

公开(公告)号：AT433581T

公开(公告)日：2009-06-15

申请号：AT03751891

申请日：2003-08-26

Applicant: IBM

Inventor： BOSE PRADIP ,  CITRON DANIEL ,  COOK PETER ,  EMMA PHILIP ,  JACOBSON HANS ,  KUDVA PRABHAKAR ,  SCHUSTER STANLEY ,  RIVERS JUDE ,  ZYUBAN VICTOR

IPC: G06F9/38 ,  G06F1/32

公开(公告)号：DE60202749T2

公开(公告)日：2005-12-29

申请号：DE60202749

申请日：2002-02-20

Applicant: IBM

Inventor： SCHUSTER STANLEY ,  COOK PETER

IPC: G06F13/42 ,  G06F9/38

Abstract: An interface between synchronous and asynchronous data transfer includes a plurality of stages coupled to each other to form a pipeline for data transfer. The plurality of stages include a first stage which performs synchronous to asynchronous data transfer, at least one intermediate stage which performs asynchronous to asynchronous data transfer and a last stage which performs asynchronous to synchronous data transfer. A synchronous clock path propagates a timing signal across the plurality of stages to enable the first and last stages to perform operations when the timing signal is present at that stage.

公开(公告)号：AU2002233528A1

公开(公告)日：2002-09-12

申请号：AU2002233528

申请日：2002-02-20

Applicant: IBM

Inventor： COOK PETER ,  SCHUSTER STANLEY

IPC: G06F13/42 ,  G06F9/38

Abstract: An interface between synchronous and asynchronous data transfer includes a plurality of stages coupled to each other to form a pipeline for data transfer. The plurality of stages include a first stage which performs synchronous to asynchronous data transfer, at least one intermediate stage which performs asynchronous to asynchronous data transfer and a last stage which performs asynchronous to synchronous data transfer. A synchronous clock path propagates a timing signal across the plurality of stages to enable the first and last stages to perform operations when the timing signal is present at that stage.