公开(公告)号：JP2006059348A

公开(公告)日：2006-03-02

申请号：JP2005233945

申请日：2005-08-12

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： COHN JOHN M ,  CULP JAMES A ,  FINKLER ULRICH A ,  HENG FOOK-LUEN ,  MARK A RABIN ,  LEE JIN FUW ,  LAAS W LIEBMANN ,  NORTHROP GREGORY A ,  SEONG NAKGEUON ,  SINGH RAMA N ,  STOK LEON ,  WOLTGENS PIETER J

IPC: G06F17/50 ,  G03F1/08 ,  H01L21/82

CPC classification number: G06F17/5081 ,  G06F17/5009 ,  G06F17/5072

Abstract: PROBLEM TO BE SOLVED: To provide a design tool which improves manufacturability of a design, namely, gives such a design that a fabricated wafer more exactly meets intended/assumed/modeled properties, at lower manufacturing cost and risk. SOLUTION: A design system for designing complex integrated circuits (ICs), a method of IC design, and program products therefor are provided. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target layout from the checked design. A data preparatory unit prepares the target layout for mask making. A pattern caching unit selectively replaces portions of the design with previously cached results for improved design efficiency. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种提高设计的可制造性的设计工具，即提供这样的设计，即制造的晶片更准确地满足预期/假设/建模性能，具有较低的制造成本和风险。

解决方案：提供了一种用于设计复杂集成电路（IC）的设计系统，一种IC设计方法及其程序产品。 布局单元接收表示网格和字形格式的部分的电路描述。 检查单元检查设计的网格和字形部分。 精心设计单元从检查的设计生成目标布局。 数据准备单元准备面具制作的目标布局。 模式高速缓存单元用先前缓存的结果有选择地替换设计的部分，以提高设计效率。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2005234571A

公开(公告)日：2005-09-02

申请号：JP2005039330

申请日：2005-02-16

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ROSENBLUTH ALAN E ,  GALLATIN GREGG M ,  GORDON RONALD L ,  SEONG NAKGEUON ,  LVOV ALEXEY Y ,  HINSBERG WILLIAM D ,  HOFFNAGLE JOHN A ,  HOULE FRANCES A ,  SANCHEZ MARTHA I

IPC: G03F1/08 ,  G03B27/54 ,  G03F7/20

CPC classification number: G03F7/705 ,  G03F1/36 ,  G03F7/70441

Abstract: PROBLEM TO BE SOLVED: To provide a fast and high-performance projection optics simulation method and system with a non-scalar (i.e. "non-Hopkins") effect taken into account. SOLUTION: A generalized bilinear kernel independent of a mask transmission function is formed to include various influences, and the kernel is processed by decomposition to compute an image including a non-scalar effect. Dominant eigenfunctions of the generalized bilinear kernel can be used to previously compute a convolution with possible polygon sectors. Then a mask transmission function can be decomposed into polygon sectors, and a weighted pre-image may be formed from a coherent sum of the pre-computed convolution for appropriate mask polygon sectors. The image at a point may be formed from the incoherent sum of the weighted pre-images over all of the dominant eigenfunctions of the generalized bilinear kernel. The resulting image can be used to perform MBOPC (model-based optical proximity correction). COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供考虑到非标量（即“非霍普金斯”）效应的快速和高性能的投影光学模拟方法和系统。 解决方案：形成独立于掩模传输功能的广义双线性内核以包含各种影响，并且通过分解处理内核以计算包括非标量效应的图像。 广义双线性核的主要本征函数可用于预先计算可能的多边形扇区的卷积。 然后，掩模传输功能可以被分解成多边形扇区，并且可以从针对适当的屏蔽多边形扇区的预先计算的卷积的相干和形成加权的预先图像。 一点上的图像可以由广义双线性核的所有主要特征函数上的加权预图像的非相干和形成。 所得到的图像可用于执行MBOPC（基于模型的光学邻近校正）。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：DE602006006088D1

公开(公告)日：2009-05-14

申请号：DE602006006088

申请日：2006-07-25

Applicant: IBM

Inventor： DORIS BRUCE ,  COSTRINI GREGORY ,  GLUSCHENKOV OLEG ,  LEONG MEIKEI ,  SEONG NAKGEUON

IPC: H01L27/11 ,  H01L21/8244

Abstract: The present invention relates to a semiconductor device structure that includes at least one SRAM cell formed in a substrate. Such SRAM cell comprises two pull-up transistors, two pull-down transistors, and two pass-gate transistors. The pull-down transistors and the pass-gate transistors are substantially similar in channel widths and have substantially similar source-drain doping concentrations, while the SRAM cell has a beta ratio of at least 1.5. The substrate preferably comprises a hybrid substrate with at two isolated sets of regions, while carrier mobility in these two sets of regions differentiates by a factor of at least about 1.5. More preferably, the pull-down transistors of the SRAM cell are formed in one set of regions, and the pass-gate transistors are formed in the other set of regions, so that current flow in the pull-down transistors is larger than that in the pass-gate transistors.

公开(公告)号：AT427563T

公开(公告)日：2009-04-15

申请号：AT06777968

申请日：2006-07-25

Applicant: IBM

Inventor： DORIS BRUCE ,  COSTRINI GREGORY ,  GLUSCHENKOV OLEG ,  LEONG MEIKEI ,  SEONG NAKGEUON

IPC: H01L27/11 ,  H01L21/8244

Abstract: The present invention relates to a semiconductor device structure that includes at least one SRAM cell formed in a substrate. Such SRAM cell comprises two pull-up transistors, two pull-down transistors, and two pass-gate transistors. The pull-down transistors and the pass-gate transistors are substantially similar in channel widths and have substantially similar source-drain doping concentrations, while the SRAM cell has a beta ratio of at least 1.5. The substrate preferably comprises a hybrid substrate with at two isolated sets of regions, while carrier mobility in these two sets of regions differentiates by a factor of at least about 1.5. More preferably, the pull-down transistors of the SRAM cell are formed in one set of regions, and the pass-gate transistors are formed in the other set of regions, so that current flow in the pull-down transistors is larger than that in the pass-gate transistors.