公开(公告)号：EP1927128A4

公开(公告)日：2009-01-28

申请号：EP06804017

申请日：2006-09-22

Applicant: IBM

Inventor： CHIDAMBARRAO DURESETI ,  DOKUMACI OMER ,  GLUSCHENKOV OLEG ,  BELYANSKY MICHAEL

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/51

CPC classification number: H01L29/512 ,  H01L21/26586 ,  H01L21/31155 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66583

Abstract: The present invention provides a semiconductor structure having at least one CMOS device in which the Miller capacitances, i-e., overlap capacitances, are reduced and the drive current is improved. The inventive structure includes a semiconductor substrate having at least one overlaying gate conductor, each of the at least one overlaying gate conductors has vertical edges; a first gate oxide located beneath the at least one overlaying gate conductor, the first gate oxide not extending beyond the vertical edges of the at least overlaying gate conductor; and a second gate oxide located beneath at least a portion of the at one overlaying gate conductor. In accordance with the present invention, the first gate oxide and the second gate oxide are selected from high k oxide-containing materials and low k oxide-containing materials, and the first gate oxide is higher k than the second gate oxide or vice-versa.

公开(公告)号：EP1382064A4

公开(公告)日：2008-05-07

申请号：EP01987463

申请日：2001-12-27

Applicant: IBM

Inventor： DOKUMACI OMER ,  GLUSCHENKOV OLEG ,  HEDGE SURYANARAYAN G ,  KAPLAN RICHARD ,  KHARE MUKESH

IPC: H01L21/3205 ,  H01L29/786 ,  H01L21/265 ,  H01L21/28 ,  H01L21/31 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L21/28176 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/28247 ,  H01L29/42368 ,  H01L29/4941

Abstract: A method of enhancing the rate of transistor gate corner oxidation, without significantly increasing the thermal budget of the overall processing scheme is provided. Specifically, the method of the present invention includes implanting ions into gate corners of a Si-containing transistor, and exposing the transistor including implanted transistor gate corners to an oxidizing ambient. The ions employed in the implant step include Si; non-retarding oxidation ions such as O, Ge, As, B, P, In, Sb, Ga, F, C1, He, Ar, Kr, and Xe; and mixtures thereof.

公开(公告)号：EP2108192A4

公开(公告)日：2009-12-30

申请号：EP07855285

申请日：2007-12-20

Applicant: IBM

Inventor： LIU YAOCHANG ,  CHIDAMBARRAO DURESETI ,  RIM KERN ,  GLUSCHENKOV OLEG ,  MO RENEE T ,  HOLT JUDSON R

IPC: H01L27/10 ,  H01L21/336 ,  H01L21/82 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L21/823864 ,  H01L21/76886 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/3279 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

公开(公告)号：EP1683187A4

公开(公告)日：2008-08-27

申请号：EP04810633

申请日：2004-11-09

Applicant: IBM

Inventor： DORIS BRUCE B ,  BELYANSKY MICHAEL P ,  BOYD DIANE C ,  CHIDAMBARRAO DURESETI ,  GLUSCHENKOV OLEG

IPC: H01L29/49 ,  H01L21/28 ,  H01L21/324 ,  H01L21/336 ,  H01L21/8238

CPC classification number: H01L29/7845 ,  H01L21/26513 ,  H01L21/28035 ,  H01L21/28167 ,  H01L21/28247 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/1083 ,  H01L29/4925 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659

Abstract: A method of fabricating a semiconductor device structure, includes: providing a substrate, providing an electrode on the substrate, forming a recess in the electrode, the recess having an opening, disposing a small grain semiconductor material within the recess, covering the opening to contain the small grain semiconductor material, within the recess, and then annealing the resultant structure.

公开(公告)号：EP1864319A4

公开(公告)日：2009-11-18

申请号：EP06748845

申请日：2006-03-29

Applicant: IBM

Inventor： BELYANSKY MICHAEL P ,  GLUSCHENKOV OLEG ,  LI YING ,  MALLIKARJUNAN ANUPAMA

IPC: H01L21/26

CPC classification number: H01L21/3185 ,  C23C16/345 ,  C23C16/45523 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/7833 ,  H01L29/7843

Abstract: A method for increasing the level of stress for amorphous thin film stressors by means of modifying the internal structure of such stressors is provided. The method includes first forming a first portion of an amorphous film stressor material on at least a surface of a substrate, said first portion having a first state of mechanical strain defining a first stress value. After the forming step, the first portion of the amorphous film stressor material is densified such that the first state of mechanical strain is not substantially altered, while increasing the first stress value. In some embodiments, the steps of forming and densifying are repeated any number of times to obtain a preselected and desired thickness for the stressor.

公开(公告)号：EP1825509A4

公开(公告)日：2009-04-15

申请号：EP05853786

申请日：2005-12-13

Applicant: IBM

Inventor： CHIDAMBARRAO DURESETI ,  DOKUMACI OMER H ,  DORIS BRUCE B ,  GLUSCHENKOV OLEG ,  ZHU HUILONG

IPC: H01L21/84 ,  H01L27/01

CPC classification number: H01L21/84 ,  H01L27/1203 ,  H01L29/7843 ,  Y10S438/938

Abstract: The present invention provides a strained-Si structure, in which the nFET regions of the structure are strained in tension and the pFET regions of the structure are strained in compression. Broadly the strained-Si structure comprises a substrate; a first layered stack atop the substrate, the first layered stack comprising a compressive dielectric layer atop the substrate and a first semiconducting layer atop the compressive dielectric layer, wherein the compressive dielectric layer transfers tensile stresses to the first semiconducting layer, and a second layered stack atop the substrate, the second layered stack comprising an tensile dielectric layer atop the substrate and a second semiconducting layer atop the tensile dielectric layer, wherein the tensile dielectric layer transfers compressive stresses to the second semiconducting layer. The tensile dielectric layer and the compressive dielectric layer preferably comprise nitride, such as Si3N4.

公开(公告)号：EP1588403A4

公开(公告)日：2010-03-24

申请号：EP04702490

申请日：2004-01-15

Applicant: IBM

Inventor： RADENS CARL ,  DOKUMACI OMER H ,  DORIS BRUCE B ,  GLUSCHENKOV OLEG ,  MANDELMAN JACK A

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L29/49

CPC classification number: H01L29/4983 ,  H01L21/26586 ,  H01L21/28105 ,  H01L29/66484 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7831 ,  H01L29/7836 ,  Y10S257/90

公开(公告)号：EP1872409A4

公开(公告)日：2009-12-30

申请号：EP06750619

申请日：2006-04-19

Applicant: IBM

Inventor： ZHU WENJUAN ,  CHUDZIK MICHAEL P ,  GLUSCHENKOV OLEG ,  PARK DAE-GYU ,  SEKIGUCHI AKIHISA

IPC: H01L29/78 ,  H01L21/28 ,  H01L21/336 ,  H01L29/51

CPC classification number: H01L21/28185 ,  H01L21/28097 ,  H01L21/28229 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/517

公开(公告)号：JP2004153256A

公开(公告)日：2004-05-27

申请号：JP2003347641

申请日：2003-10-06

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： GLUSCHENKOV OLEG ,  HEGDE SURYANARAYAN G ,  TEWS HELMUT H

IPC: H01L21/316 ,  H01L21/314 ,  H01L21/321 ,  H01L29/78

CPC classification number: H01L21/3144 ,  H01L21/3141 ,  H01L21/32105

Abstract: PROBLEM TO BE SOLVED: To provide an improved method for growing high quality oxide on a composite face of a silicon substrate having at least two crystal orientations.
SOLUTION: Formation of a vertical MOS transistor on a silicon wafer or formation of another 3 dimensional integrated circuit structure expose two faces having at least two different crystal orientations. Since interatomic spaces are different for the different faces, the oxides on the different crystal faces grow at essentially different speeds. When the silicon is heated in a nitrogen-containing atmosphere to form a thin layer of nitrogen, and then the oxide is grown via a thin nitrided layer, variations of the thickness of the oxide are reduced to less than 1 %.
COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2004214631A

公开(公告)日：2004-07-29

申请号：JP2003400729

申请日：2003-11-28

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DOKUMACI OMER H ,  GLUSCHENKOV OLEG ,  BELYANKSY MICHAEL ,  DORIS BRUCE B

IPC: H01J1/312 ,  H01L21/00 ,  H01L21/033 ,  H01L21/205 ,  H01L21/425 ,  H01L29/06 ,  H01L29/76 ,  H01L31/0336 ,  H01L31/0352

CPC classification number: B82Y30/00 ,  B82Y10/00 ,  B82Y20/00 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/0332 ,  H01L21/0337 ,  H01L31/0352

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a uniform layer structure, including an ultra-thin layer of amorphous silicon and a thermal oxide thereof. SOLUTION: In one side surface, the present invention is a method for forming the nano-laminate of an oxidized silicon on a substrate. In the other side surface, the invention is a method for forming a patterned hard mask on the substrate. The patterned hard mask includes the nano-laminate of a silicon and the oxidized silicon. The methods are characterized by the oxidization of an amorphous silicon layer using atomic oxygen. COPYRIGHT: (C)2004,JPO&NCIPI