公开(公告)号：DE69227432D1

公开(公告)日：1998-12-03

申请号：DE69227432

申请日：1992-08-01

Applicant: IBM

Inventor： DHONG SANG H ,  SHIN HYUN J ,  HWANG WEI

IPC: G11C11/407 ,  G11C5/14 ,  G11C8/08 ,  H01L21/822 ,  H01L27/04

Abstract: A voltage generator comprising a regulator for controlling said on-chip generator which produces a boost voltage VBST supplied to one of two inputs to each of a plurality of word line drivers in a memory array, the other input to each of said word line drivers receiving a power supply voltage VDD. Said voltage regulator comprising: means for generating a reference voltage VREF; first differential means (33) for producing a transition voltage VX from said reference voltage VREF and said power supply voltage VDD, said transition voltage being representative of a fluctuation in said power supply voltage; first transistor means (QP3) for comparing said power supply voltage VDD with said boost voltage VBST; second transistor (QP5) means for comparing said transition voltage VX with said reference voltage VREF; and a latching comparator (44) coupled to receive the signal outputs from said first transistor (QP3) and said second transistor (QP5), said latching comparator outputting a boost voltage control signal for said on-chip voltage generator, said control signal operating to define the following boost voltage: VBST = - VREF + VDD - VX.

公开(公告)号：DE69227432T2

公开(公告)日：1999-06-02

申请号：DE69227432

申请日：1992-08-01

Applicant: IBM

Inventor： DHONG SANG H ,  SHIN HYUN J ,  HWANG WEI

IPC: G11C11/407 ,  G11C5/14 ,  G11C8/08 ,  H01L21/822 ,  H01L27/04

Abstract: A voltage generator comprising a regulator for controlling said on-chip generator which produces a boost voltage VBST supplied to one of two inputs to each of a plurality of word line drivers in a memory array, the other input to each of said word line drivers receiving a power supply voltage VDD. Said voltage regulator comprising: means for generating a reference voltage VREF; first differential means (33) for producing a transition voltage VX from said reference voltage VREF and said power supply voltage VDD, said transition voltage being representative of a fluctuation in said power supply voltage; first transistor means (QP3) for comparing said power supply voltage VDD with said boost voltage VBST; second transistor (QP5) means for comparing said transition voltage VX with said reference voltage VREF; and a latching comparator (44) coupled to receive the signal outputs from said first transistor (QP3) and said second transistor (QP5), said latching comparator outputting a boost voltage control signal for said on-chip voltage generator, said control signal operating to define the following boost voltage: VBST = - VREF + VDD - VX.