公开(公告)号：DE3278892D1

公开(公告)日：1988-09-15

申请号：DE3278892

申请日：1982-05-28

Applicant: IBM

Inventor： SPENCER DANA ROYCE

IPC: G06F12/08

公开(公告)号：DE1183721B

公开(公告)日：1964-12-17

申请号：DEJ0020947

申请日：1961-12-02

Applicant: IBM

Inventor： SPENCER DANA ROYCE

IPC: G06F3/09 ,  H03K5/135 ,  H04L5/24

Abstract: 987,442. Electric selective signalling. INTERNATIONAL BUSINESS MACHINES CORPORATION. Nov. 24, 1961 [Dec. 12, 1960], No. 42109/61. Heading G4H. Data pulses issuing from a keyboard on which is entered sales information (date, quantity, type of goods) are sampled by pulses of such frequency that at least one falls completely within a data pulse and an information pulse is transmitted to a utilization device in response to the first sample pulse which falls completely within a data pulse. The significance of numerical items transmitted by depressing keys on a keyboard 104 is indicated by previously pressing a categorizing button on a console 103, such as date button DT, quantity button Q and so on. Before any data is entered a "data ready" button DR is pressed. Each of the keys of the keyboard 104 is sampled in turn and the value of a depressed key is indicated by data pulses in a seven-bit code on parallel lines. While a data pulse is on any of the lines conductor 115 is up and 116 down. While a sample pulse exists line 113 is up and 114 down. The and circuits A 1 to A 5 in response to coincidence of positive inputs produce a negative output. Or circuits -O 1 , -O 2 , in response to a negative input produce a positive output. Operation of keyboard. The "data ready" button DR is first depressed, followed by a category button, say "date" DT, and the keys of number keyboard 104. The "terminate category" button TC is then pressed. The DR and the next required category button is then depressed, the appropriate number entered and the TC button operated. When all items have been entered, the "terminate entry" (TE) button is operated. If sampling shows that the DR button has been depressed the category buttons are sampled to find which has been operated. The keys of keyboard 104 operate sequentially and pass a long pulse MK on to appropriate lines as data pulses. When pulse MK is passed by button TC the category buttons are a gain scanned, or if button TE passes MK the operation stops. Gating data pulses: The first complete sample pulse falling within a data pulse opens gates 110. In such a case line 115 is already up and -O 2 giving a negative output which is inverted at I 2 to send positive one input to and circuit A 2 . When line 113 goes up all inputs to A 2 are positive and a negative output results. This is inverted by I 1 to open gates 110, and also sets the latch comprised of and A 1 and or -O 1 . When line 113 goes down the latch remains set and line 114 goes up operating and A 5 . The resultant positive output of or circuit -O 2 is inverted by I 2 to prevent and A 2 from passing any later sample pulses while the same data pulse is present. When the next sample pulse arrives A 4 operates and maintains the low output of I 2 . This situation is only changed when line 115 goes down, indicating the end of the data pulse, and causes the latch A 1 ,-O 1 to be unset. If a sample pulse arrives when there is no data pulse and A 3 operates and I 2 produces a low output to disenable and A 2 . Then, a data pulse starting while line 113 is still up has no effect on the circuits.

公开(公告)号：GB989867A

公开(公告)日：1965-04-22

申请号：GB3899563

申请日：1963-10-03

Applicant: IBM

Inventor： GRANITO GERRY DAVID ,  SMITH LUCIUS DERWARD ,  SPENCER DANA ROYCE ,  STAFFORD THOMAS SANDERSON

IPC: G06F13/22

Abstract: 989, 867. Electric digital data storage. INTERNATIONAL BUSINESS MACHINES CORPORATION. Oct. 3, 1963, No. 38995/63. Heading G4C. A storage device receives massages, each including destination identifying data, assembles them in selected locations in an addressable store, scans a plurality of transmission circuits associated with the destinations and selects the storage location containing the data to be transmitted via each transmission circuit as it is scanned. The device operates as an automatic buffer store which connectes between a central computer and a number of remote devices without interruption at either interface. As shown, thirty transmission lines are scanned by a line control 114, as described in Specification 963,959, and as each line is scanned a corresponding control word is transferred to a control word register 116. The control word includes a "general buffer area" in which the address in store 102 which has been allotted to the particular line being scanned, is stored. At each scan a further bit of each message from each active destination device is added to the corresponding storage location so that each message is built up ready for transmission to the central computer as described in Specification 969,314. Messages to be transmitted from the central computer to one of the remote stations are receives serially by bit from the computer on a line 108, are demodulated at 109, converted to parallel by bit serial by character in a shift register and passed to a storage register 111. They are then applied through a terminal address decoder 200 to a terminal address store, and also to a data register 101 during step 31 of the counter 118, at which time a further control word is in the register 116. The output message is compiled in the memory 102 at an address stipulated by the control word. When the message is completed an end of message detector 203 sets a trigger 204. When the line on which transmission is required is scanned, a compare circuit operates to enable AND gates 207, 208 so that either a gate 210 or a gate 214 is opened, so that the address within the store 102 of the data to be transmitted is entered in the control word "general buffer area", or if this is in use, in the "buffer area wait" portion of the control word. When the "general buffer area" is cleared at the completion of a transmission, AND and INVERT logic operates a gate 216 to gate the address stored in the "buffer area wait" section of the control word to the "general buffer area" section so that transmission of the next message can be initiated.

公开(公告)号：DE2355814A1

公开(公告)日：1974-06-12

申请号：DE2355814

申请日：1973-11-08

Applicant: IBM

Inventor： SPENCER DANA ROYCE

IPC: G06F12/10 ,  G06F12/08 ,  G06F9/06 ,  G06F13/06

Abstract: In a storage hierarchy system in which a limited number of blocks of data in a backing store are held in a smaller buffer store, channel requests for access to storage are made to the buffer store. A circuit monitors the channel requests to the buffer store and detects various conditions that indicate that the channel may make a forthcoming request to a block that is held in the backing store but not in the buffer store. When such a request is detected, the circuit produces a dummy request to transfer the block to the buffer store before the actual channel request to this block. The invention reduces the average access time to the store and it reduces the likelihood of a condition called channel overrun that may occur when buffer storage space is not available when requested by the channel.