公开(公告)号：DE1279980B

公开(公告)日：1968-10-10

申请号：DEJ0030950

申请日：1966-05-28

Applicant: IBM

Inventor： STAFFORD THOMAS SANDERSON ,  BURNSTINE DONALD CHARLES ,  PAUL GERARD THOMAS ,  ROGASKI JOHN RICHARD

IPC: G06F9/46 ,  G06F11/20 ,  G06F15/177 ,  G06F15/16

公开(公告)号：GB1280488A

公开(公告)日：1972-07-05

申请号：GB5401670

申请日：1970-11-13

Applicant: IBM

Inventor： IV WILLIAM ALBERT CLARK ,  DAVIES CHARLES TUDOR JR ,  SALMOND KENT ADAMS ,  STAFFORD THOMAS SANDERSON

IPC: G06F17/30 ,  H03M7/30

Abstract: 1280488 Data storage INTERNATIONAL BUSINESS MACHINES CORP 13 Nov 1970 [31 Dec 1969] 54016/70 Heading G4C A data processing system for generating a multilevel compressed index includes means for receiving an input stream of uncompressed keys, means for generating low-level compressed keys from the input stream of uncompressed keys, means for assembling the low-level compressed keys in low-level index blocks, means for registering for a next higher level a last of the uncompressed keys for each current low-level index block, and means for generating a higherlevel compressed key from the last two of the uncompressed keys currently provided for the last two low-level index blocks by the registering means. A multi-level index is derived from the input stream of uncompressed keys by taking these, segmented into multi-key blocks, as the lowest level, and for each block (of this lowest level) taking the first key of the next block to represent it in the next higher level, each subsequently higher level containing the last key of each block of the respective next lower level to represent that block, the highest (apex) level having only one block. Concurrently, a pointer is associated with each key and each key is compressed. In the lowest level the pointer points to a corresponding data block (which includes its respecitve uncompressed key, besides data), and in each higher level the pointer points to the corresponding block of the respective next lower level. Each compressed key, besides the pointer, includes one or more key bytes (from the uncompressed key), a length byte (specifying the number of key bytes) and a factor byte (specifying the number of key bytes in the uncompressed key to high-order of those included in the compressed key). Compression of a given key in a given level I is done on the basis of: E BI viz. the number of byte positions to high order of the highest-order unequal byte position when the uncompressed key is compared with the preceding uncompressed key in the same level I, E AI viz. same as E BI except that the comparison is between the preceding uncompressed key mentioned and its preceding uncompressed key in the same level, E BO viz. same as E BI except that the comparison is done between the uncompressed key and the uncompressed key preceding it where the former appears in the lowest level, E AO viz. same as E BO except that the comparison is between the preceding uncompressed key mentioned and its preceding uncompressed key in the lowest level. For the lowest level, a quantity T is set to zero if and only if the length byte of the preceding compressed key was zero. A quantity S is defined as E BI -E AI for the level concerned (E BO -E AO for the lowest level). For a compressed key in the lowest level, the length byte L and the factor byte F are given values as follows (and bytes are selected from the uncompressed key for incorporation in the compressed key in accordance with them): (a) If S is zero and T is non-zero, or if S is negative, L is zero and F is E BO plus one. (b) If S and T are zero, L is one and F is E BO . (c) If S is positive and T is zero, L is S plus one and F is E AO . (d) If S is positive and T is non-zero, L is S and F is E AO plus one. For a compressed key in a level I other than the lowest level: (a) If S is zero or negative, L is E BO -E BI plus one and F is E BI . (b) If S is positive, L is E BO -E BI and F is E AI plus one. Searching in the index requires searching of only one block per level.

公开(公告)号：GB1153420A

公开(公告)日：1969-05-29

申请号：GB2217768

申请日：1968-05-10

Applicant: IBM

Inventor： ARULPRAGASAM JEGANANDARAJ AMAL ,  HOCKINGS MICHAEL LE HEGARAT KI ,  MINSHULL JOHN FRANCIS ,  PINNELL MARTIN COXWELL ,  STAFFORD THOMAS SANDERSON

IPC: G06F9/48

Abstract: 1,153,420. Computer interrupt. INTERNATIONAL BUSINESS MACHINES CORP. 10 May, 1968, No. 22177/68. Heading G4A. In a data processing system, an interrupt condition causes the status of the current programme to be stored in a first area, a second area to be allocated to a new programme, and the address of the first area to be entered into the second area. In a two-processor microprogramme-controlled system, the highest priority interrupt request not masked by a status register selects a double-word from a (stored) interrupt list according to the class of interrupt. The doubleword includes a bit-pair and an address. If the bit-pair is 01, 10 or 11, the address is that of an interrupt class list. If the bit-pair is 01, the interrupt code (which gives details of the interrupt) is shifted and used to select another double-word from the interrupt class list. If the bit-pair is 10, the interrupt code is decremented by a so-called "mask" in the interrupt class list and one of two double-words selected from this list according as the result is negative or not. If the bit-pair is 11, the interrupt code is ANDed with the "mask" and one of the two doublewords selected according as the result is zero or not. If the bit-pair is 00, the address is that of a status load block. In this way a sequence of one or more double-words is selected until one is reached with the bit-pair 00 to obtain the address of a status load block. In the above, if the interrupt code is decremented, it is the decremented interrupt code which is used, if necessary, in connection with the next double-word, but if it is ANDed, it is the code before ANDing which is used. The status load block is used to initialize the system to execute the programme for dealing with the interrupt, after storing the current status data (relating to the interrupted programme) in a current programme status block (storage area), to enable subsequent resumption of the interrupted programme. A programme status block is obtained for the new programme, the address of this block being obtained from the head of the interrupt list which specifies the address of the first block of a free list of such blocks, each block in the list containing the address of the next so that they are chained together. The "first block" address in the interrupt list is then updated. While the interrupt list is being used by one processor, a lock byte and the identity of the processor are stored in it (the list) to prevent the other processor using it and to enable this processor to find out why use is prevented. The programme status block (which is loaded With status data for its programme when that programme is interrupted) holds interrupt masking bits, storage protection key (for comparison with a key associated with each block of storage to prevent access unless they are equal or one is zero), instruction length indicator, indication of conditions which will cause branch, next instruction address, indications of which local storage registers have had their contents saved (determined by the doubleword with bit-pair 00 referred to above), addresses of locations where various registers can be dumped in the event of an interrupt, the address of the programme status block of the previously running programme, class of interrupt, identity of processor to which the current interruption is related, interrupt code, and extended interrupt code giving more information on the interrupt. Provision is made for dealing with exhaustion of the free list. Conventional types of interrupt are described. The interrupt list, interrupt class lists and status load blocks are settable under control of a supervisor programme. Besides the two processors, the system includes two memories with a unified addressing scheme and the effective configuration of the system is controlled by configuration control data stored in the various units.

公开(公告)号：GB989867A

公开(公告)日：1965-04-22

申请号：GB3899563

申请日：1963-10-03

Applicant: IBM

Inventor： GRANITO GERRY DAVID ,  SMITH LUCIUS DERWARD ,  SPENCER DANA ROYCE ,  STAFFORD THOMAS SANDERSON

IPC: G06F13/22

Abstract: 989, 867. Electric digital data storage. INTERNATIONAL BUSINESS MACHINES CORPORATION. Oct. 3, 1963, No. 38995/63. Heading G4C. A storage device receives massages, each including destination identifying data, assembles them in selected locations in an addressable store, scans a plurality of transmission circuits associated with the destinations and selects the storage location containing the data to be transmitted via each transmission circuit as it is scanned. The device operates as an automatic buffer store which connectes between a central computer and a number of remote devices without interruption at either interface. As shown, thirty transmission lines are scanned by a line control 114, as described in Specification 963,959, and as each line is scanned a corresponding control word is transferred to a control word register 116. The control word includes a "general buffer area" in which the address in store 102 which has been allotted to the particular line being scanned, is stored. At each scan a further bit of each message from each active destination device is added to the corresponding storage location so that each message is built up ready for transmission to the central computer as described in Specification 969,314. Messages to be transmitted from the central computer to one of the remote stations are receives serially by bit from the computer on a line 108, are demodulated at 109, converted to parallel by bit serial by character in a shift register and passed to a storage register 111. They are then applied through a terminal address decoder 200 to a terminal address store, and also to a data register 101 during step 31 of the counter 118, at which time a further control word is in the register 116. The output message is compiled in the memory 102 at an address stipulated by the control word. When the message is completed an end of message detector 203 sets a trigger 204. When the line on which transmission is required is scanned, a compare circuit operates to enable AND gates 207, 208 so that either a gate 210 or a gate 214 is opened, so that the address within the store 102 of the data to be transmitted is entered in the control word "general buffer area", or if this is in use, in the "buffer area wait" portion of the control word. When the "general buffer area" is cleared at the completion of a transmission, AND and INVERT logic operates a gate 216 to gate the address stored in the "buffer area wait" section of the control word to the "general buffer area" section so that transmission of the next message can be initiated.

公开(公告)号：DE1179738B

公开(公告)日：1964-10-15

申请号：DEJ0023069

申请日：1963-01-29

Applicant: IBM

Inventor： BARKER HAROLD DESMOND ,  STAFFORD THOMAS SANDERSON

IPC: G06F3/00 ,  G06F7/02 ,  G06F13/38 ,  H04J3/16 ,  H04L5/22 ,  H04L13/08

Abstract: 963,959. Telegraphy. INTERNATIONAL BUSINESS MACHINES CORPORATION. Jan. 2, 1963 [Feb. 1, 1962], No. 245/63. Heading H4P. The invention provides a device which can receive low speed data simultaneously from a plurality of sources, pass the data at high speed to a central computer, receive data from the computer, and pass it to the respective data source; each data source has one of a plurality of predetermined transmission rates, data being handled in blocks of 100 characters. Each data source line is scanned during a fraction of the smallest bit, and the device establishes a data sampling rate for each line compatible with the transmission rate of the data received on that line. The apparatus accommodates up to 30 incoming lines but the system is described here with reference to the Figure which shows the data received on 5 lines. The data on a particular line has always one of three bit rates, designated Type A, Type B and Type C. The frequency of an oscillator is a multiple of each of the bit rates; in the example the repetition frequencies of Types A : B : C are 5: 7 : 14. The output 201 of the oscillator feeds counters A, B, C, which respectively count to 5, 7 and 14. Counter C is arranged so that only odd counts are effective, the representation of counter C output therefore being as shown. All 30 lines are scanned sequentially during period 202. Each incoming line is connected to an A, B, or C terminal by way of a plugboard, dependent upon the data bit rate. Upon receipt of the start of a data block the count of the relevant counter is added to part of a control word, derived from a store. Consider Line 1 (Type B bit rate). The start 208 arrives as counter B indicates 2. To this count is added a predetermined number, 3. For Type A data this number is 2 and for Type B is 3. The total, 5, is stored in the control word, and each time counter B reaches this total, which is at the approximate mid-point of each bit, line 1 is sampled and the sample passed to a data store. The control words are changed synchronously with the line scan and each word indicates the time at which the line is to be sampled (as above described), the address in the data store to which the received character is to be fed prior to read-out of a complete block at high speed to the computer, the message block, and parity and other information. The data store also contains data received from the computer for transfer to the lines.