公开(公告)号：JP2002237541A

公开(公告)日：2002-08-23

申请号：JP2001369481

申请日：2001-12-04

Applicant: IBM

Inventor： COOLBAUGH DOUGLAS DUANE ,  DUNN JAMES STUART ,  ST ONGE STEPHEN ARTHUR

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06

Abstract: PROBLEM TO BE SOLVED: To provide a method of forming a low-cost polysilicon-to-polysilicon capacitor, which is used in a CMOS or Bi CMOS integrated circuit, and which is not complicated. SOLUTION: The method, which is integrated with a Bi CMOS process and which forms the polysilicon-to-polysilicon capacitor, comprises a step in which the lower-part plate electrode of the capacitor is formed, while the gate electrode of a CMOS transistor is stuck and a step in which an upper-part SiGe plate electrode is formed, while the SiGe base region of a heterojunction bipolar transistor is grown.

公开(公告)号：JP2002009163A

公开(公告)日：2002-01-11

申请号：JP2001113510

申请日：2001-04-12

Applicant: IBM

Inventor： DOUGLAS D KUURUBAAGU ,  DUNN JAMES STUART ,  ST ONGE STEPHEN ARTHUR

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/94

Abstract: PROBLEM TO BE SOLVED: To provide a stacked double polysilicon/MOS capacitor useful as the component of a BiCMOS device including a semiconductor substrate forming a first conductivity-type area on the surface. SOLUTION: A gate oxide overlapped on the first conductivity-type area is formed on the semiconductor substrate. A first polysilicon layer doped with an N type dopant or a P type dopant is formed at least on a gate oxide layer. A dielectric layer is formed on the first polysilicon layer. A second polysilicon layer doped with the same dopant as the first polysilicon layer or a different dopant is formed on the dielectric layer.

公开(公告)号：DE60128028T2

公开(公告)日：2008-01-03

申请号：DE60128028

申请日：2001-02-22

Applicant: IBM

Inventor： COOLBAUGH DOUGLAS D ,  DUNN JAMES STUART ,  ST ONGE STEPHEN ARTHUR

IPC: H01L27/04 ,  H01L29/92 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/94

Abstract: A stacked Poly-Poly/MOS capacitor useful as a component in a BiCMOS device comprising a semiconductor substrate having a region of a first conductivity-type formed in a surface thereof; a gate oxide formed on said semiconductor substrate overlaying said region of first conductivity-type; a first polysilicon layer formed on at least said gate oxide layer, said first polysilicon layer being doped with an N or P-type dopant; a dielectric layer formed on said first polysilicon layer; and a second polysilicon layer formed on said dielectric layer, said second polysilicon layer being doped with the same or different dopant as the first polysilicon layer.

公开(公告)号：ES2281379T3

公开(公告)日：2007-10-01

申请号：ES01000026

申请日：2001-02-22

Applicant: IBM

Inventor： COOLBAUGH DOUGLAS D ,  DUNN JAMES STUART ,  ST ONGE STEPHEN ARTHUR

IPC: H01L27/04 ,  H01L29/92 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/94

Abstract: Un condensador Poli-Poli/MOS apilado comprende: un sustrato (10) semiconductor que tiene una región de un primer tipo (12) de conductividad presente en una superficie del mismo; un óxido (16) de puerta presente encima de dicha región de primer tipo de conductividad; una primera capa (18) de electrodo, no estando dicha primera capa (18) de electrodo en contacto con dicha región de primer tipo (12) de conductividad y que sirve como ambos, un electrodo superior de un semiconductor de óxido de metal y una electrodo de base de un condensador; una capa (20) de dieléctrico presente sobre una porción de dicha primera capa (18) de electrodo; y una segunda capa (22) de electrodo presente en dicha capa (20) de dieléctrico, sirviendo dicha segunda capa (22) de electrodo como un electrodo superior de dicho condensador, caracterizado porque la primera capa (18) de electrodo encapsula las superficies vertical y horizontal expuestas de dicho óxido (16) de puerta y al menos una de dichas primera y segunda capas (18, 22) de electrodo que comprenden SiGe.

公开(公告)号：DE60128028D1

公开(公告)日：2007-06-06

申请号：DE60128028

申请日：2001-02-22

Applicant: IBM

Inventor： COOLBAUGH DOUGLAS D ,  DUNN JAMES STUART ,  ST ONGE STEPHEN ARTHUR

IPC: H01L27/04 ,  H01L29/92 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/94

Abstract: A stacked Poly-Poly/MOS capacitor useful as a component in a BiCMOS device comprising a semiconductor substrate having a region of a first conductivity-type formed in a surface thereof; a gate oxide formed on said semiconductor substrate overlaying said region of first conductivity-type; a first polysilicon layer formed on at least said gate oxide layer, said first polysilicon layer being doped with an N or P-type dopant; a dielectric layer formed on said first polysilicon layer; and a second polysilicon layer formed on said dielectric layer, said second polysilicon layer being doped with the same or different dopant as the first polysilicon layer.

公开(公告)号：DE60120897D1

公开(公告)日：2006-08-03

申请号：DE60120897

申请日：2001-09-24

Applicant: IBM

Inventor： COOLBAUGH DOUGLAS DUANE ,  DUNN JAMES STUART ,  ST ONGE STEPHEN ARTHUR

IPC: H01L21/8249 ,  H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8222 ,  H01L21/8248 ,  H01L27/06

Abstract: A method is provided for fabricating a poly-poly capacitor integrated with a BiCMOS process. This includes forming a lower plate electrode of a poly-poly capacitor during deposition of a gate electrode of a CMOS transistor. An upper SiGe plate electrode is then formed during growth of a SiGe base region of a heterojunction bipolar transistor.

公开(公告)号：AT331299T

公开(公告)日：2006-07-15

申请号：AT01308085

申请日：2001-09-24

Applicant: IBM

Inventor： COOLBAUGH DOUGLAS DUANE ,  DUNN JAMES STUART ,  ST ONGE STEPHEN ARTHUR

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06

Abstract: A method is provided for fabricating a poly-poly capacitor integrated with a BiCMOS process. This includes forming a lower plate electrode of a poly-poly capacitor during deposition of a gate electrode of a CMOS transistor. An upper SiGe plate electrode is then formed during growth of a SiGe base region of a heterojunction bipolar transistor.

公开(公告)号：AT360890T

公开(公告)日：2007-05-15

申请号：AT01000026

申请日：2001-02-22

Applicant: IBM

Inventor： COOLBAUGH DOUGLAS D ,  DUNN JAMES STUART ,  ST ONGE STEPHEN ARTHUR

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/94 ,  H01L29/92

Abstract: A stacked Poly-Poly/MOS capacitor useful as a component in a BiCMOS device comprising a semiconductor substrate having a region of a first conductivity-type formed in a surface thereof; a gate oxide formed on said semiconductor substrate overlaying said region of first conductivity-type; a first polysilicon layer formed on at least said gate oxide layer, said first polysilicon layer being doped with an N or P-type dopant; a dielectric layer formed on said first polysilicon layer; and a second polysilicon layer formed on said dielectric layer, said second polysilicon layer being doped with the same or different dopant as the first polysilicon layer.

公开(公告)号：DE60120897T2

公开(公告)日：2006-12-21

申请号：DE60120897

申请日：2001-09-24

Applicant: IBM

Inventor： COOLBAUGH DOUGLAS DUANE ,  DUNN JAMES STUART ,  ST ONGE STEPHEN ARTHUR

IPC: H01L21/8249 ,  H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8222 ,  H01L21/8248 ,  H01L27/06

Abstract: A method is provided for fabricating a poly-poly capacitor integrated with a BiCMOS process. This includes forming a lower plate electrode of a poly-poly capacitor during deposition of a gate electrode of a CMOS transistor. An upper SiGe plate electrode is then formed during growth of a SiGe base region of a heterojunction bipolar transistor.