公开(公告)号：JP2008153684A

公开(公告)日：2008-07-03

申请号：JP2008018552

申请日：2008-01-30

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHU JACK OON ,  COOLBAUGH DOUGLAS DUANE ,  DUNN JAMES STUART ,  GREENBERG DAVID ,  HARAME DAVID ,  JAGANNATHAN BASANTH ,  JOHNSON ROBB ALLEN ,  LANZEROTTI LOUIS ,  SCHONENBERG KATHRYN TURNER ,  WUTHRICH RYAN WAYNE

IPC: H01L21/331 ,  H01L21/205 ,  H01L29/737

CPC classification number: H01L29/66242 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L29/1004 ,  H01L29/161 ,  H01L29/7378

Abstract: PROBLEM TO BE SOLVED: To provide a method of forming a SiGe bipolar transistor substantially excluding dislocation defects present between an emitter and collector region.
SOLUTION: This forming method includes the steps of: (a) providing a structure including at least a bipolar device region, wherein the bipolar device region includes at least a first conductive type collector region 52 formed in a semiconductor substrate; (b) making a SiGe base region 54 deposit on the collector region, wherein carbon is continuously grown over the whole collector region and the whole SiGe base region during deposition; and (c) forming the emitter region 56 patterned on the SiGe base region.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种形成SiGe双极晶体管的方法，其基本上排除了发射极和集电极区域之间存在的位错缺陷。 该形成方法包括以下步骤：（a）提供包括至少双极器件区域的结构，其中双极器件区域至少包括形成在半导体衬底中的第一导电类型集电极区域52; （b）使SiGe基区54沉积在集电区上，其中在沉积期间碳在整个集电区和整个SiGe基区连续生长; 和（c）形成在SiGe基区上图案化的发射极区56。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2002231727A

公开(公告)日：2002-08-16

申请号：JP2002004201

申请日：2002-01-11

Applicant: IBM

Inventor： COOLBAUGH DOUGLAS DUANE ,  DUPUIS MARK D ,  GALLAGHER MATTHEW D ,  PETER J JEAYES ,  PHILIPS BRETT A

IPC: H01L29/73 ,  H01L21/20 ,  H01L21/331 ,  H01L29/732 ,  H01L29/737

Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing an SiGe heterojunction bipolar transistor which reduces the SiGe base resistance. SOLUTION: An SiGe heterojunction bipolar transistor comprises a semiconductor substrate with a collector and a subcollector. The collector and the subcollector are formed between isolation regions existing within the substrate. Each isolation region comprises a recessed surface and a nonrecessed surface and these surfaces are formed by a lithography and an etching. An SiGe layer is formed on the substrate and the recessed and nonrecessed surfaces of each isolation region. The SiGe layer comprises a polycrystalline Si region and an SiGe base region. A patterned insulating layer is formed on the SiGe base region and moreover, an emitter is formed on the patterned insulating layer and comes into contact with the SiGe base region through an emitter window aperture.

公开(公告)号：JP2002237541A

公开(公告)日：2002-08-23

申请号：JP2001369481

申请日：2001-12-04

Applicant: IBM

Inventor： COOLBAUGH DOUGLAS DUANE ,  DUNN JAMES STUART ,  ST ONGE STEPHEN ARTHUR

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06

Abstract: PROBLEM TO BE SOLVED: To provide a method of forming a low-cost polysilicon-to-polysilicon capacitor, which is used in a CMOS or Bi CMOS integrated circuit, and which is not complicated. SOLUTION: The method, which is integrated with a Bi CMOS process and which forms the polysilicon-to-polysilicon capacitor, comprises a step in which the lower-part plate electrode of the capacitor is formed, while the gate electrode of a CMOS transistor is stuck and a step in which an upper-part SiGe plate electrode is formed, while the SiGe base region of a heterojunction bipolar transistor is grown.

公开(公告)号：JP2001267432A

公开(公告)日：2001-09-28

申请号：JP2001051096

申请日：2001-02-26

Applicant: IBM

Inventor： COOLBAUGH DOUGLAS DUANE ,  FREEMANN GREGORY GOWER ,  SUBANNA SESHADRI

IPC: H01L21/331 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8249 ,  H01L27/04 ,  H01L27/06 ,  H01L29/73 ,  H01L29/737

Abstract: PROBLEM TO BE SOLVED: To provide a method for fabricating a polysilicon-polysilicon capacitor for use in a CMOS or BiCMOS integrated circuit simply and inexpensively. SOLUTION: The method for forming a polysilicon-polysilicon capacitor 49, an MOS transistor 18, and a bipolar transistor 48 simultaneously on a substrate 10 comprises a step for forming a first polysilicon layer on the substrate 10 and patterning it in order to form the first plate electrode of the capacitor 49 and the electrode of the MOS transistor 18, and a step for forming a second polysilicon layer on the substrate 10 and patterning it in order to form the second plate electrode of the capacitor 49 and the electrode of the bipolar transistor 48.

公开(公告)号：DE10107012A1

公开(公告)日：2001-09-13

申请号：DE10107012

申请日：2001-02-15

Applicant: IBM

Inventor： COOLBAUGH DOUGLAS DUANE ,  FREEMANN GREGORY GOWER ,  SUBANNA SESHADRI

IPC: H01L21/331 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8249 ,  H01L27/04 ,  H01L27/06 ,  H01L29/73 ,  H01L29/737 ,  H01L27/08

Abstract: The simultaneous formation of a poly-poly capacitor, a MOS transistor and a bipolar transistor on a substrate (10) comprises applying and structuring a first layer made from polycrystalline silicon on the substrate to form a first plate electrode of the capacitor and an electrode of the MOS transistor; and applying and structuring a second layer made from a polycrystalline silicon on the substrate to form a second plate electrode of the capacitor and an electrode of the bipolar transistor. The second polycrystalline layer is made from SiGe-polycrystalline silicon. An Independent claim is also included for the production of a poly-poly capacitor. Preferred Features: The electrode of the MOS transistor comprises a polycrystalline gate (20) formed on a gate oxide (22). The gate oxide is formed on the surface of the substrate and the substrate has source and drain regions (14) below the polycrystalline gate.

公开(公告)号：DE60120897D1

公开(公告)日：2006-08-03

申请号：DE60120897

申请日：2001-09-24

Applicant: IBM

Inventor： COOLBAUGH DOUGLAS DUANE ,  DUNN JAMES STUART ,  ST ONGE STEPHEN ARTHUR

IPC: H01L21/8249 ,  H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8222 ,  H01L21/8248 ,  H01L27/06

Abstract: A method is provided for fabricating a poly-poly capacitor integrated with a BiCMOS process. This includes forming a lower plate electrode of a poly-poly capacitor during deposition of a gate electrode of a CMOS transistor. An upper SiGe plate electrode is then formed during growth of a SiGe base region of a heterojunction bipolar transistor.

公开(公告)号：AT331299T

公开(公告)日：2006-07-15

申请号：AT01308085

申请日：2001-09-24

Applicant: IBM

Inventor： COOLBAUGH DOUGLAS DUANE ,  DUNN JAMES STUART ,  ST ONGE STEPHEN ARTHUR

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06

Abstract: A method is provided for fabricating a poly-poly capacitor integrated with a BiCMOS process. This includes forming a lower plate electrode of a poly-poly capacitor during deposition of a gate electrode of a CMOS transistor. An upper SiGe plate electrode is then formed during growth of a SiGe base region of a heterojunction bipolar transistor.

公开(公告)号：PL362710A1

公开(公告)日：2004-11-02

申请号：PL36271001

申请日：2001-11-23

Applicant: IBM

Inventor： CHU JACK OON ,  COOLBAUGH DOUGLAS DUANE ,  DUNN JAMES STUART ,  GREENBERG DAVID ,  HARAME DAVID ,  JAGANNATHAN BASANTH ,  JOHNSON ROBB ALLEN ,  LANZEROTTI LOUIS ,  SCHONENBERG KATHRYN TURNER ,  WUTHRICH RYAN WAYNE

IPC: H01L21/331 ,  H01L29/737

Abstract: A SiGe bipolar transistor containing substantially no dislocation defects present between the emitter and collector region and a method of forming the same are provided. The SiGe bipolar transistor includes a collector region of a first conductivity type; a SiGe base region formed on a portion of said collector region; and an emitter region of said first conductivity type formed over a portion of said base region, wherein said collector region and said base region include carbon continuously therein. The SiGe base region is further doped with boron.

公开(公告)号：CZ20032066A3

公开(公告)日：2003-11-12

申请号：CZ20032066

申请日：2001-11-23

Applicant: IBM

Inventor： CHU JACK OON ,  COOLBAUGH DOUGLAS DUANE ,  DUNN JAMES STUART ,  GREENBERG DAVID ,  HARAME DAVID ,  JAGANNATHAN BASANTH ,  JOHNSON ROBB ALLEN ,  LANZEROTTI LOUIS ,  SCHONENBERG KATHRYN TURNER ,  WUTHRICH RYAN WAYNE

IPC: H01L21/331 ,  H01L29/737

Abstract: A SiGe bipolar transistor containing substantially no dislocation defects present between the emitter and collector region and a method of forming the same are provided. The SiGe bipolar transistor includes a collector region of a first conductivity type; a SiGe base region formed on a portion of said collector region; and an emitter region of said first conductivity type formed over a portion of said base region, wherein said collector region and said base region include carbon continuously therein. The SiGe base region is further doped with boron.

公开(公告)号：PL203317B1

公开(公告)日：2009-09-30

申请号：PL36271001

申请日：2001-11-23

Applicant: IBM

Inventor： CHU JACK OON ,  COOLBAUGH DOUGLAS DUANE ,  DUNN JAMES STUART ,  GREENBERG DAVID ,  HARAME DAVID ,  JAGANNATHAN BASANTH ,  JOHNSON ROBB ALLEN ,  LANZEROTTI LOUIS ,  SCHONENBERG KATHRYN TURNER ,  WUTHRICH RYAN WAYNE

IPC: H01L21/331 ,  H01L29/737