-
公开(公告)号：JPH07271339A
公开(公告)日：1995-10-20
申请号：JP30721094
申请日：1994-12-12
Applicant: IBM
Inventor： GARII JIEIMUZU MOORUSU , SUTEFUAN PATORITSUKU TONPUSON
Abstract: PURPOSE: To provide a method and device by which the displaying efficiency of characters can be improved, when the characters are displayed on the display of a data processing system. CONSTITUTION: A character-displaying method includes a plurality of processes for displaying characters on the display 22 of a data processing system 10. Each process requires various quantities of processor resources for displaying the characters on the display. Such a process that the characters can be displayed on the display more efficiently than the other processes is selected out of the processes. The characters can be displayed when font data in the system memory 16 of the data processing system are cached. The type bit map to a specific character can be moved to a graphics adapter 20 from a cache, by utilizing such a permanent move instruction that can also be utilized by a CPU 14. The characters are moved to the adapter 20, through a fixed scanning line base, containing all character strings in the entire width of the character or in one line.
-
公开(公告)号：JPH07210141A
公开(公告)日：1995-08-11
申请号：JP26657094
申请日：1994-10-31
Applicant: IBM
Abstract: PURPOSE: To provide a method and device for supporting the virtualization of a VGA graphics mode during the native mode operation of an XGA display adapter. CONSTITUTION: In order to make the virtualization of a VGA graphics mode possible during the native mode operation of an XGA display adapter, the adapter is selectively enabled by making VGA graphics supporting hardware 208 and a specific VGA register accessible. The XGA display adapter contains an XGA operation mode register having three control bits and the register is selectively written by means of application software so as to permit or inhibit a virtual VGA function. When the virtual VGA function is permitted, a logic circuit in a host interface 200 discriminates whether each video memory access is not native memory access, but contains virtual VGA memory access, by checking CPU addresses related to each video memory access.
-
公开(公告)号：JPH0635849A
公开(公告)日：1994-02-10
申请号：JP10637393
申请日：1993-05-07
Applicant: IBM
Inventor： SUTEFUAN PATORITSUKU TONPUSON
IPC: G06F13/362 , G06F13/30 , G06F13/364 , G06F13/376
Abstract: PURPOSE: To realize an efficient and effective bus preferential use control on a system bus to which plural bus master devices are connected. CONSTITUTION: Preferential use logics 30 for recognizing a system bus control request that a second bus master device gives while a first bus master device controls the system bus, for causing the first bus master device to abort the control of the system bus and for leaving control to the second bus master device are provided for the respective bus master devices.
-
公开(公告)号：JPH05188892A
公开(公告)日：1993-07-30
申请号：JP14339792
申请日：1992-05-09
Applicant: IBM
Inventor： SUTEFUAN PATORITSUKU TONPUSON
IPC: G06F3/153 , G06F3/14 , G06F5/06 , G06F5/10 , G06F5/12 , G09G1/16 , G09G5/00 , G09G5/36 , G09G5/393 , G09G5/395
Abstract: PURPOSE: To provide a video system having plural programmable operation modes and a refresh buffer. CONSTITUTION: A pack level detecting circuit 202 recognize a time when the pack level of a first-in first-out buffer(FIFO) 201 reaches a previously fixed level being specifiedly 3, 5 or 6 double words or the level more than that. A central processing unit can write new video data in a video memory 113 by a processor access circuit. Whenever the present pack level is equal to below a min. pack level which is set by a pack level selecting circuit 205, the processing unit access circuit is in a disenable state. The central processing unit performs access to the video memory 113 only when min. level data exists in FIFO 201, and the min. level data is selected in accordance with a present operation mode.
-
-
-
Search Results
4
records
(took 0.018 seconds)
