公开(公告)号：JPH07210143A

公开(公告)日：1995-08-11

申请号：JP27648894

申请日：1994-11-10

Applicant: IBM

Inventor： DAAUIN PII RATSUKUREI ,  AARU MAIKERU UESUTO

IPC: G09G5/02 ,  G09G5/06 ,  G09G5/08 ,  G09G5/38

Abstract: PURPOSE: To provide a method and device for adjusting the color of a sprite by making the sprite clearly visible regardless of underlying display data. CONSTITUTION: The color of a sprite overlaying a picture displayed on a video display device is derived by only adjusting the highest bit MST of each pixel data component of red, green, and blue of an underlying picture by means of a sprite control logic circuit provided on a pallet DAC 322. The sprite control logic circuit contains first, second, and third multiplexers MUXs and each multiplexer has a first input which receives the MSB of each pixel data component of red, green and blue of the underlying picture and a second input which receives the outputs of first, second, and third XOR gates. Each XOR gate has a first input which receives the MSB of each pixel data component of red, green, and blue of the underlying picture and a second input which receives data from a sprite RAM 324.

公开(公告)号：JPH07210141A

公开(公告)日：1995-08-11

申请号：JP26657094

申请日：1994-10-31

Applicant: IBM

Inventor： SUTEFUAN PATORITSUKU TONPUSON ,  DAAUIN PII RATSUKUREI ,  SHIYAAUTSUDO BURANNON

IPC: G09G5/393 ,  G09G5/00 ,  G09G5/36 ,  G09G5/39 ,  G09G5/395

Abstract: PURPOSE: To provide a method and device for supporting the virtualization of a VGA graphics mode during the native mode operation of an XGA display adapter. CONSTITUTION: In order to make the virtualization of a VGA graphics mode possible during the native mode operation of an XGA display adapter, the adapter is selectively enabled by making VGA graphics supporting hardware 208 and a specific VGA register accessible. The XGA display adapter contains an XGA operation mode register having three control bits and the register is selectively written by means of application software so as to permit or inhibit a virtual VGA function. When the virtual VGA function is permitted, a logic circuit in a host interface 200 discriminates whether each video memory access is not native memory access, but contains virtual VGA memory access, by checking CPU addresses related to each video memory access.

公开(公告)号：JPH05292331A

公开(公告)日：1993-11-05

申请号：JP7402992

申请日：1992-03-30

Applicant: IBM

Inventor： AOKI YUTAKA ,  AIDA YUJI ,  DAAUIN PII RATSUKUREI

IPC: G06T9/00 ,  H03M7/46 ,  H04N1/419 ,  G06F15/66

Abstract: PURPOSE: To improve the data writing speed to a bit map memory at the time of decoding a run length code by reducing the data writing frequency to the bit map memory by providing a skip entry. CONSTITUTION: An external storage device 8, such as the CD-ROM, etc., is connected to a CPU 2 through a system bus 4 and an SCSI interface 6. A system memory 10 is connected to the bus and, in addition, a bit map memory 14 and a display device 16 are also connected to the bus 4 through a video controller 12. The storage device 8 stores data for display expressed in accordance with a run length code. After the CPU 2 reads the run length code data stored in the storage device 8 and holds the data in the memory 10, a video controller 12 decodes the data and writes the decoded data in a memory 14. The controller 12 reads out the data from the memory 14 and transfers the data to the display device 16 after converting the data into video signals. Therefore, the data writing speed to the memory 14 can be improved by reducing the data writing frequency to the memory 14.