公开(公告)号：US3708766A

公开(公告)日：1973-01-02

申请号：US3708766D

申请日：1970-12-31

Applicant: IBM

Inventor： SHA R ,  TANG D

IPC: H04L25/03 ,  H04B3/04

CPC classification number: H04L25/03133

Abstract: An automatic equalizer with extremely fast convergence is disclosed. The weight setting procedure or algorithm is basically an iterative operation which can be conveniently expressed by cascaded equalizers. One form of the apparatus utilized consists of a plurality of equalizer stages which have their tap settings changed after successive iterations (the first iteration adjusts the first equalizer stage, the second iteration adjusts the second equalizer stage and so on) such that after n iterations a given initial distortion D is reduced to at most D2 . The algorithm involved and the method of operating the equalizer is also disclosed.

Abstract translation: 公开了一种具有极快收敛性的自动均衡器。 权重设置过程或算法基本上是迭代操作，可以方便地通过级联均衡器来表示。 所使用的装置的一种形式包括多个均衡器级，它们在连续迭代之后改变其抽头设置（第一迭代调整第一均衡器级，第二次迭代调整第二均衡器级等），使得在n次迭代之后 给定初始失真D减少到最多D2。 还公开了涉及的算法和操作均衡器的方法。

公开(公告)号：US3792356A

公开(公告)日：1974-02-12

申请号：US3792356D

申请日：1971-12-27

Applicant: IBM

Inventor： KOBAYASHI H ,  TANG D

IPC: H03H15/00 ,  H04L25/03 ,  H04L25/497 ,  H04B3/14

CPC classification number: H04L25/03057 ,  H04L25/03146

Abstract: The present invention relates to a new receiver structure for the equalization of partial-response or correlative level coding systems in which the main equalizer and quantizer are embedded inside the inverse filter. The main embedded filter primarily accomplishes equalization of signal distortion in the tail portion of the received signal. According to a further aspect of the invention, a separate precursor equalizer may be utilized in front of the receiver structure in situations where the front end or precursor intersymbol interference is not negligible. According to one additional aspect of the invention where the number of precursor interference terms is small, a certain amount of precursor equalization may be included in the inverse filter portion of the main receiver structure. The receiver structure has a wide variety of applications and will function well with a number of different correlative coding schemes. Further, the main equalizer embedded within the receiver structure may be of the fixed, automatic or adaptive type as are well known in the art. The source of the correlatively encoded data containing undesired intersymbol interference due to characteristics of the channel or noise may be either a transmission line or, for example, a magnetic recording and pickup system utilizing the NRZI recording scheme.

Abstract translation: 本发明涉及用于均衡部分响应或相关级编码系统的新的接收机结构，其中主均衡器和量化器嵌入在反相滤波器内。 主嵌入式滤波器主要实现接收信号尾部信号失真的均衡。 根据本发明的另一方面，在前端或前体符号间干扰不可忽略的情况下，可以在接收机结构的前面使用单独的前体均衡器。 根据本发明的另一方面，其中前导干扰项的数量较少，在主接收机结构的逆滤波器部分中可以包括一定量的前驱均衡。 接收机结构具有广泛的应用，并且能够与许多不同的相关编码方案一起工作。 此外，嵌入在接收机结构内的主均衡器可以是本领域公知的固定，自动或自适应类型。 由于信道或噪声的特性，包含不期望的符号间干扰的相关编码数据的来源可以是传输线，或例如使用NRZI记录方案的磁记录和拾取系统。

公开(公告)号：US3716807A

公开(公告)日：1973-02-13

申请号：US3716807D

申请日：1971-05-24

Applicant: IBM

Inventor： SHA R ,  TANG D

IPC: H04L25/03 ,  H04B3/04

CPC classification number: H04L25/03133

Abstract: A recursive automatic equalizer with extremely fast convergence is disclosed. The equalizer includes a plurality of equalizer stages connected in cascade which first reduces impulse response of the communication channel to substantially zero. The front portion or sidelobe is reduced to substantially zero distortion by adjusting the tap settings of successive equalizer stages after successive iterations (the first iteration adjusts the tap settings of the first equalizer stage, the second iteration adjusts the tap settings of the second equalizer stage, and so on) such that after n iterations a given initial distortion D is reduced to substantially zero. The tap setting algorithm involved and the method of operating the cascaded equalizer is disclosed. Finally, after n iterations, the output signal which can be described by the function 1-A(n) is modified by the reciprocal of the foregoing function and, is this manner, the rear or trailing portion of an input signal which is to be equalized has its rear sidelobe distortion reduced to substantially zero leaving only the desired main pulse. Apparatus for modifying the trailing or rear end of a pulse to be equalized is also disclosed.

Abstract translation: 公开了具有极快收敛的递归自动均衡器。 均衡器包括级联的多个均衡器级，其首先将通信信道的脉冲响应减小到基本为零。 通过在连续迭代之后调整连续均衡器级的抽头设置（第一次迭代调整第一均衡器级的抽头设置，第二次迭代调整第二均衡器级的抽头设置），前部或副瓣被减小到基本上零失真， 等等），使得在n次迭代之后，给定的初始失真D被减小到基本为零。 公开了涉及的抽头设置算法和操作级联均衡器的方法。 最后，在n次迭代之后，可以由函数1-A（n）描述的输出信号由上述函数的倒数修改，并且这样，将要输入的信号的后部或尾部 其均衡的后旁瓣失真减小到基本为零，仅留下期望的主脉冲。 还公开了用于修改待均衡的脉冲的尾端或后端的装置。

公开(公告)号：CA926012A

公开(公告)日：1973-05-08

申请号：CA100734

申请日：1970-12-16

Applicant: IBM

Inventor： TANG D ,  KOBAYASHI HISASHI

IPC: H04L1/00 ,  H04L25/48 ,  H04L25/497

Abstract: 1277158 Data transmission INTERNATIONAL BUSINESS MACHINES CORP 13 Nov 1970 [30 Dec 1969] 54015/70 Heading H4P A data transmission system uses correlation encoding with resulting increase in the number of signal value levels. In Fig. 2, an input signal train A(D)= a 0 + a 1 + D + a 2 D 2 + ... (where D is a time delay operator) where each signal can have any of m levels, is preceded at 10 (to prevent propagation of a chain of errors from a single error in the received transmission) by dividing by G(D)= g 0 + g 1 D + g 2 D 5 + ... and taking the resulting levels mod m, to give a train B(D)=b 0 + b 1 D + b 2 D 2 + .... This is correlatively encoded, 12, by multiplying by G(D) to give C(D)=c 0 + c 1 D + c 2 D 2 + ... in which each level can have any of M (greater than m) levels. C(D) is transmitted over a channel 14 and the received signal C 1 (D) decoded, 18, by dividing by G(D) to give B 1 (D) which in the absence of error equals B(D) and so has only m levels. If there are more than m levels, a level detector 22 (two thresholders feeding an OR gate) produces an error signal to give a warning or cause retransmission and inhibition of a decoder 20 which otherwise multiplies B 1 (D) by G(D) and takes the resulting levels mod m to give A 1 (D), which is equal to A(D) in the absence of errors. A modified system combines 10 and 12 into a unitary encoder, combines 18, 20, 22 into a unitary decoder and precedes the latter with a level splitter which standardizes the received levels to their nominal values after detecting them with thresholders. Fig. 4 shows the unitary encoder, assuming G(D)=g 0 + g 1 D + g 2 D 2 + ... 5 + g N D N , and is self-explanatory, the notation being as before. The unitary decoder is like Fig. 4 except that the mod m detector 34 follows the adder 46, the result from multiplier 36 is not taken mod m, and the output from this multiplier is also fed to a level detector to produce the error signal. If G(D) is 1 - D 2 , then b k =a k + b k-2 , mod m, and c k = b k - b k-2 . A(D) may have m = 3 and result from a preliminary 2-to-3 level transformation (no details).