公开(公告)号：DE19527592A1

公开(公告)日：1997-01-30

申请号：DE19527592

申请日：1995-07-28

Applicant: IBM

Inventor： TAST HANS WERNER DIPL ING ,  GETZLAFF KLAUS JOERG DIPL ING ,  WILLE UDO DIPL ING ,  MUENSTER HANS-JUERGEN

IPC: G06F12/0855 ,  G06F12/08

Abstract: The data processor system includes a processor with cache memory (3) for the processor, an address map (6) belonging to the cache store and a buffer store (10) for intermediate storage of data lines. The address map for registering the address of a data line in the cache memory is designed so that registering of the address is carried out prior to full storage of the relevant data line in the cache memory. The processor system includes a logic (14) circuit for controlling the buffer store (10) and controlling the output of data, of a data line whose address is already registered, but not fully stored in the cache memory, from the buffer store.