公开(公告)号：DE4307139A1

公开(公告)日：1994-09-08

申请号：DE4307139

申请日：1993-03-06

Applicant: IBM

Inventor： FISCHER WOLFGANG DIPL ING ,  GETZLAFF KLAUS JOERG DIPL ING ,  KURZ BRIGITTE ,  TAST HANS-WERNER DIPL ING ,  WILLE UDO DIPL ING ,  WITHELM BIRGIT

IPC: G06F13/362 ,  G06F15/17 ,  G06F13/36

Abstract: A method of making processors (PU0 to Pn) of a multiprocessor system (MP) quiescent, or of serialising bus assignments for the individual processors, is described. This serialisation becomes necessary if one or more processors simultaneously want to execute commands which require uninterrupted ownership of the bus for as long as they are being executed, e.g. to prevent damage to the integrity of data. For this purpose, a quiescent-making network (QN), which connects all processors, is used. Processors which execute such atomic commands receive their bus assignment on a priority basis. The processor with the highest rank puts its competitors into conditional branch command loops (BC loops), in which they wait for a specified condition, e.g. "QN not blocked" (QU+). If this condition is fulfilled, e.g. after the end of an atomic command, the processor with the next lower priority receives the bus. Processors which are executing other commands are forced into a no-operation state (NOP), from which they are released after completion of the atomic command of another processor, to resume their interrupted commands.

公开(公告)号：DE4307139C2

公开(公告)日：1997-02-13

申请号：DE4307139

申请日：1993-03-06

Applicant: IBM

Inventor： FISCHER WOLFGANG DIPL ING ,  GETZLAFF KLAUS JOERG DIPL ING ,  KURZ BRIGITTE ,  TAST HANS-WERNER DIPL ING ,  WILLE UDO DIPL ING ,  WITHELM BIRGIT

IPC: G06F13/362 ,  G06F15/17 ,  G06F13/364 ,  G06F9/46

公开(公告)号：DE19527592A1

公开(公告)日：1997-01-30

申请号：DE19527592

申请日：1995-07-28

Applicant: IBM

Inventor： TAST HANS WERNER DIPL ING ,  GETZLAFF KLAUS JOERG DIPL ING ,  WILLE UDO DIPL ING ,  MUENSTER HANS-JUERGEN

IPC: G06F12/0855 ,  G06F12/08

Abstract: The data processor system includes a processor with cache memory (3) for the processor, an address map (6) belonging to the cache store and a buffer store (10) for intermediate storage of data lines. The address map for registering the address of a data line in the cache memory is designed so that registering of the address is carried out prior to full storage of the relevant data line in the cache memory. The processor system includes a logic (14) circuit for controlling the buffer store (10) and controlling the output of data, of a data line whose address is already registered, but not fully stored in the cache memory, from the buffer store.