公开(公告)号：CA2021832A1

公开(公告)日：1991-04-03

申请号：CA2021832

申请日：1990-07-24

Applicant: IBM

Inventor： KEENER DON S ,  MCNEILL ANDREW B ,  WACHTEL EDWARD I

IPC: G06F13/362 ,  G06F13/22 ,  G06F13/24

Abstract: Apparatus and method for increasing efficiency of command execution from a host processor (11) over an SCSI bus (14). Arbitration, selection and message out functions of SCSI protocol are implemented using a background arbitration state machine (32). Additional protocol functions are implemented in a foreground state machine (26). When the host processor (11) issues a command for access to the SCSI bus (14), the background state machine (32) can be programmed before the foreground machine (26) completes the protocol function for a previous command. Thus, the background state machine (32) is ready to arbitrate for access to the bus (14) at the very next bus free condition.

公开(公告)号：CA2092631A1

公开(公告)日：1993-12-20

申请号：CA2092631

申请日：1993-03-12

Applicant: IBM

Inventor： KEENER DON S ,  MCNEILL ANDREW B ,  SCHEIERN KEVIN L ,  NEWSOM THOMAS H ,  VOORHEES RICHARD W ,  WACHTEL EDWARD I

IPC: G06F13/36 ,  G06F13/40 ,  G06F13/16

Abstract: Arrangements are disclosed for physically partitioning a bus having a well defined architecture as a physical entity, wherein the partitioning is logically transparent to a computer and devices which communicate through the bus and serves to avoid problems potentially arising because of the scope of actions permitted by the architecture. A typical bus architecture to which present arrangements have relevance is that associated with SCSI (Small Computer System Interface) buses. The potential problems allowed to occur architecturally involve: (a) exposures of data security/integrity; (b) excessive signal degradation due to use of signal rates which although allowed by the architecture are inappropriate for a particular bus loading environment also allowed by the architecture; (c) restrictions preventing parallel transfer of data between the computer and multiple storage devices; (d) restrictions unduly limiting the number of devices attachable to one logical bus path (one input-output channel of the computer). The disclosed arrangement partitions the bus into two or more physical entities which to the computer appears as one logical entity.

公开(公告)号：BR9204660A

公开(公告)日：1993-06-22

申请号：BR9204660

申请日：1992-12-03

Applicant: IBM

Inventor： MCNEILL ANDREW B ,  WACHTEL EDWARD I

IPC: G06F13/10 ,  G06F13/38 ,  G06F13/20

公开(公告)号：CA2085973A1

公开(公告)日：1993-06-21

申请号：CA2085973

申请日：1992-12-21

Applicant: IBM

Inventor： MCNEILL ANDREW B JR ,  WACHTEL EDWARD I

IPC: G06F13/10 ,  G06F13/38